5754eade4a
The patch updates platform_is_resuming() API such that platform resume state is determined from the saved state (CBMEM) instead of checking PMC registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early) ramstage. coreboot sends DISCONNECT IPC command which times out during resume (S3) if system has servoV4 connected on port0. The issue occurs only during the first cycle of resume (S3) test cycle after cold boot due to side effect of platform_is_resuming() API that is not determining the resume (S3) state correctly in ramstage. PM1_STS and PM1_CNT register gets cleared at the start of ramstage. platform_is_resuming() function was checks the cleared register value and fails the condition of resume (S3) resulting in sending DISCONNECT IPC command. Checking the platform resume state from the CBMEM saved state using acpe_get_sleep_type() function helps cross verify the system previous state at the later part of ramstage. localhost ~ # cbmem -c | grep ERROR [ERROR] EC returned error result code 3 [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:0 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:1 to initial state [ERROR] GENERIC: 0.0 missing read_resources [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0xd0 failed [ERROR] PMC: Failed sending PCI Enumeration Done Command BUG=b:227289581 TEST=Verified system boots to OS and verified below tests on Redrix (ADL-P) and Nivviks (ADL-N) 1. coreboot doesn't send the DISCONNECT during S3 resume 2. suspend S3 passes with both suzyq and servoV4 connected 3. After S3 resume, system detects the pen drive with Superspeed 4. After system resumes from S3, hot-plug the pen drive, system detects the pen drive Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| 3rdparty | ||
| configs | ||
| Documentation | ||
| LICENSES | ||
| payloads | ||
| spd | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| .mailmap | ||
| AUTHORS | ||
| COPYING | ||
| gnat.adc | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| toolchain.inc | ||
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.