1d6484a858
Change-Id: I9d54d0923a595734a84256ddcafb9dae17615cb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43348 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include "sandybridge.h"
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#include <stddef.h>
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#include <stdint.h>
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static uintptr_t smm_region_start(void)
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{
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/* Base of TSEG is top of usable DRAM */
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return pci_read_config32(HOST_BRIDGE, TSEGMB);
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}
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void *cbmem_top_chipset(void)
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{
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return (void *)smm_region_start();
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}
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return ALIGN_DOWN(smm_region_start(), 1 * MiB);
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}
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static size_t northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram = (uintptr_t)cbmem_top();
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/*
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* Cache 8MiB below the top of ram. On sandybridge systems the top of
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* RAM under 4GiB is the start of the TSEG region. It is required to
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* be 8MiB aligned. Set this area as cacheable so it can be used later
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* for ramstage before setting up the entire RAM as cacheable.
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*/
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postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
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/*
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* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
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* is where the TSEG region resides. However, it is not restricted
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* to SMM mode until SMM has been relocated. By setting the region
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* to cacheable it provides faster access when relocating the SMM
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* handler as well as using the TSEG region for other purposes.
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*/
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postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK);
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}
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