40783f2862
Change-Id: If9efbde5939913b67852b377dd84cd4de1ec2718 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
18 lines
375 B
C
18 lines
375 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/early_spi.h>
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#include "i82801jx.h"
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void bootblock_early_southbridge_init(void)
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{
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enable_spi_prefetching_and_caching();
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i82801jx_setup_bars();
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/* Enable upper 128bytes of CMOS. */
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RCBA32(0x3400) = (1 << 2);
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i82801jx_lpc_setup();
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}
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