bae9f85ddb
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
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RootHub
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USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
59 lines
2.5 KiB
Text
Executable file
59 lines
2.5 KiB
Text
Executable file
%{
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/*
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* sconfig, coreboot device tree compiler
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*
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* Copyright (C) 2010 coresystems GmbH
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* written by Patrick Georgi <patrick@georgi-clan.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "sconfig.tab.h"
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int linenum = 0;
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%}
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%option nodebug
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%%
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[ \t]+ {}
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#.*\n {linenum++;}
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\r?\n {linenum++;}
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chip {return(CHIP);}
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device {return(DEVICE);}
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register {return(REGISTER);}
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on {yylval.number=1; return(BOOL);}
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off {yylval.number=0; return(BOOL);}
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pci {yylval.number=PCI; return(BUS);}
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ioapic {yylval.number=IOAPIC; return(BUS);}
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pnp {yylval.number=PNP; return(BUS);}
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i2c {yylval.number=I2C; return(BUS);}
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lapic {yylval.number=APIC; return(BUS);}
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cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);}
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cpu {yylval.number=CPU; return(BUS);}
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domain {yylval.number=DOMAIN; return(BUS);}
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generic {yylval.number=GENERIC; return(BUS);}
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mmio {yylval.number=MMIO; return(BUS);}
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spi {yylval.number=SPI; return(BUS);}
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usb {yylval.number=USB; return(BUS);}
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irq {yylval.number=IRQ; return(RESOURCE);}
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drq {yylval.number=DRQ; return(RESOURCE);}
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io {yylval.number=IO; return(RESOURCE);}
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ioapic_irq {return(IOAPIC_IRQ);}
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inherit {return(INHERIT);}
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subsystemid {return(SUBSYSTEMID);}
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end {return(END);}
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= {return(EQUALS);}
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0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
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[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
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[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
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INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);}
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\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
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\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
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[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
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%%
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