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Zheng Bao 584ab84e92 The code can run on the Mahogany board, which is one of sample boards 
made by AMD. Its major features are:
 CPU:
  * AMD AM2+
  * AMD Athlon 64 x2
  * AMD Athlon 64 FX
  * AMD Athlon 64
  * AMD Sempron CPUs
 System Chipset:
  * RS780E
  * SB700
 On Board Chipset:
  * BIOS - SPI
  * Azalia CODEC - Realtek ALC888
  * LPC SuperIO - ITE8718F(GX).
  * LAN - REALTEK 8111C
  * TPM - SLB9635TT1.2
 Main Memory:
  * DDR II * 4 (Max 4GB)
 Expansion Slots:
  * PCI Express X16 slot*2 (PCI-E X8 Bus)
  * PCI Express X4 Slot*1
 Intersil PWM:
  * Controller - Intersil 6323

Note:
1. The only difference to mahogany is the CPU is changed to K8 family 10.
2. The main structure of the code is based on
   serengeti_cheetah_fam10. I am a rookie to fam10. I am still
   confused about CONFIG_HT_CHAIN_UNITID_BASE and
   CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t
   does.  And I have to modify the some fam10 code (see the patch
   ht_chain_unitid_base.patch). I dont know how to solve this. Please
   help.
   Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList().
   The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning
   of the list. The amdht wrapper needs to modify definitely.
3. With fam10 processor, the HT link can work in HT3.
4. The ACPI _PSS table is set staticly. The auto configuaration
   process doesnt seem to work correctly.
5. Currently the fam10 code in coreboot doesn't support DDR3. If you
   happen to get a board with DDR3 and you don't have the patience to wait,
   please find another board with DDR2.
6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a
   issue for a long time. I disable the compressing currently. When the problem
   is fixed, we can re-enable it.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 		2010-03-16 01:53:10 +00:00
documentation update doxygen config file to latest doxygen version 2010-02-12 11:59:37 +00:00
payloads Trivial fix, use correct define. 2010-03-08 13:08:24 +00:00
src The code can run on the Mahogany board, which is one of sample boards 2010-03-16 01:53:10 +00:00
util Make CLANG selectable in Kconfig 2010-03-16 01:17:19 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Make CLANG selectable in Kconfig 2010-03-16 01:17:19 +00:00
README Various minor fixes (trivial). 2010-02-25 16:09:53 +00:00

README 

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary
BIOS you can find in most of today's computers.

It performs just a little bit of hardware initialization and then executes
one of many possible payloads, e.g. a Linux kernel or a bootloader.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make
 * python

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
-------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.