coreboot-kgpe-d16/spd/lp5/set-1/parts_spd_manifest.generated.txt
Frank Wu 3a4e201a21 spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.

BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15 14:28:02 +00:00

21 lines
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Text

# Generated by:
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
MT62F512M32D2DR-031 WT:B,spd-1.hex
MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
H9JCNNNBK3MLYR-N6E,spd-1.hex
MT62F2G32D8DR-031 WT:B,spd-4.hex
K3LKLKL0EM-MGCN,spd-5.hex
H58G56AK6BX069,spd-3.hex
H58G66AK6BX070,spd-6.hex
MT62F1G32D4DS-031 WT:B,spd-2.hex
K3LKCKC0BM-MGCP,spd-6.hex
MT62F1G32D2DS-026 WT:B,spd-7.hex
MT62F2G32D4DS-026 WT:B,spd-8.hex
K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
H9JCNNNFA5MLYR-N6E,spd-4.hex