58c3938705
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
95 lines
2.8 KiB
ArmAsm
95 lines
2.8 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <rules.h>
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/*
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*Take the path where CAR_GLOBAL variables just need to be cleared when
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* verstage runs directly after bootblock.
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*/
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#define ROMSTAGE_AFTER_VERSTAGE \
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(IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) && \
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IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && ENV_ROMSTAGE)
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#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || ROMSTAGE_AFTER_VERSTAGE
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/*
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* This path is for stages that are post bootblock when employing
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* CONFIG_C_ENVIRONMENT_BOOTBLOCK or any intermediate stage succeeding
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* the first stage to initialize protected mode. There's no need to re-load
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* the gdt, etc as all those settings are cached within the processor. In
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* order to continue with C code execution one needs to set stack pointer and
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* clear CAR_GLOBAL variables that are stage specific.
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*/
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.section ".text._start", "ax", @progbits
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.global _start
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_start:
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/* _car_stack_end symbol is only valid when bootblock does CAR setup. */
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#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
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/* reset stack pointer to CAR stack */
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mov $_car_stack_end, %esp
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#endif
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/* clear CAR_GLOBAL area as it is not shared */
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cld
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xor %eax, %eax
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movl $(_car_global_end), %ecx
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movl $(_car_global_start), %edi
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sub %edi, %ecx
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rep stosl
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#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \
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|| (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP)))
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/* Wait for a JTAG debugger to break in and set EBX non-zero */
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xor %ebx, %ebx
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debug_spinloop:
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cmp $0, %ebx
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jz debug_spinloop
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#endif
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jmp car_stage_entry
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/* This is here for linking purposes. */
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.weak car_stage_entry
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car_stage_entry:
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1:
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jmp 1b
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#else
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/* This file assembles the start of the romstage program by the order of the
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* includes. Thus, it's extremely important that one pays very careful
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* attention to the order of the includes. */
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#include <arch/x86/prologue.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#include <cpu/x86/fpu_enable.inc>
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#if IS_ENABLED(CONFIG_SSE)
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#include <cpu/x86/sse_enable.inc>
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#endif
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/*
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* The assembly.inc is generated based on the requirements of the mainboard.
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* For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
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* processed by ROMCC and added. In non-ROMCC boards the chipsets'
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* cache-as-ram setup files would be here.
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*/
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#include <generated/assembly.inc>
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#endif
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