ef03afa405
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
269 lines
6.9 KiB
C
269 lines
6.9 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#define K8_HT_FREQ_1G_SUPPORT 1
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "cpu/amd/model_fxx/model_fxx_msr.h"
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#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
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static void hard_reset(void)
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{
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set_bios_reset();
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/* full reset */
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outb(0x0a, 0x0cf9);
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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#if 1
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/* link reset */
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outb(0x02, 0x0cf9);
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outb(0x06, 0x0cf9);
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#endif
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}
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static void memreset_setup(void)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
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#define SUPERIO_GPIO_IO_BASE 0x400
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static void sio_gpio_setup(void){
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unsigned value;
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#if 1
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/*Enable onboard scsi*/
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
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#endif
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#define K8_4RANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/raminit.c"
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#if 0
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#define ENABLE_APIC_EXT_ID 1
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#define APIC_ID_OFFSET 0x10
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#define LIFT_BSP_APIC_ID 0
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#else
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#define ENABLE_APIC_EXT_ID 0
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#endif
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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/* tyan does not want the default */
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#include "resourcemap.c"
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#if CONFIG_LOGICAL_CPUS==1
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#define SET_NB_CFG_54 1
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#include "cpu/amd/dualcore/dualcore.c"
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#else
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#include "cpu/amd/model_fxx/node_id.c"
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#endif
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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#define CK804_NUM 2
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#define CK804B_BUSN 0xc
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#define CK804_USE_NIC 1
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#define CK804_USE_ACI 1
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#include "southbridge/nvidia/ck804/ck804_early_setup.h"
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#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
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//set GPIO to input mode
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#define CK804_MB_SETUP \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
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#include "southbridge/nvidia/ck804/ck804_early_setup.c"
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static void main(unsigned long bist)
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{
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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},
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#endif
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#if SECOND_CPU
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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},
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#endif
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};
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int needs_reset;
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#if CONFIG_LOGICAL_CPUS==1
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struct node_core_id id;
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#else
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unsigned nodeid;
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#endif
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if (bist == 0) {
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/* Skip this if there was a built in self test failure */
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amd_early_mtrr_init();
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#if CONFIG_LOGICAL_CPUS==1
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set_apicid_cpuid_lo();
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id = get_node_core_id_x(); // that is initid
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#if ENABLE_APIC_EXT_ID == 1
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if(id.coreid == 0) {
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enable_apic_ext_id(id.nodeid);
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}
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#endif
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#else
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nodeid = get_node_id();
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#if ENABLE_APIC_EXT_ID == 1
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enable_apic_ext_id(nodeid);
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#endif
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#endif
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enable_lapic();
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init_timer();
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#if CONFIG_LOGICAL_CPUS==1
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#if ENABLE_APIC_EXT_ID == 1
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#if LIFT_BSP_APIC_ID == 0
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if( id.nodeid != 0 )
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#endif
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lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
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#endif
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if(id.coreid == 0) {
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if (cpu_init_detected(id.nodeid)) {
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asm volatile ("jmp __cpu_reset");
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}
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distinguish_cpu_resets(id.nodeid);
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}
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#else
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#if ENABLE_APIC_EXT_ID == 1
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#if LIFT_BSP_APIC_ID == 0
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if(nodeid != 0)
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#endif
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lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
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#endif
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if (cpu_init_detected(nodeid)) {
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asm volatile ("jmp __cpu_reset");
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}
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distinguish_cpu_resets(nodeid);
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#endif
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if (!boot_cpu()
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#if CONFIG_LOGICAL_CPUS==1
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|| (id.coreid != 0)
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#endif
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) {
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stop_this_cpu();
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}
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}
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lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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sio_gpio_setup();
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setup_s2895_resource_map();
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needs_reset = setup_coherent_ht_domain();
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#if CONFIG_LOGICAL_CPUS==1
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start_other_cores();
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#endif
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needs_reset |= ht_setup_chains_x();
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needs_reset |= ck804_early_setup_x();
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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enable_smbus();
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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}
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