Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
..
acpi	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
variants	sb/intel/i82801gx: Detect if the southbridge supports AHCI	2019-06-06 10:38:22 +00:00
acpi_tables.c
board_info.txt
cmos.default	mb/*/*/cmos.default: Decrease debug_level to 'Debug'	2018-08-15 18:39:17 +00:00
cmos.layout	nb/intel/x4x: Use parallel MP init	2019-01-23 14:47:53 +00:00
cstates.c
data.vbt
dsdt.asl	{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h	2019-03-13 04:17:46 +00:00
gma-mainboard.ads	mb/*/*: Enable libgfxinit on x4x boards	2018-06-14 09:40:20 +00:00
hda_verb.c
Kconfig	mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree	2018-11-16 09:45:43 +00:00
Kconfig.name	src/mb/asrock/g41c-gs: Add variant g41m-s3	2018-09-28 09:56:17 +00:00
Makefile.inc	mb/asrock/g41c-gs: Link separate gpio.c files	2018-09-18 23:13:44 +00:00
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00