597ff87574
This patch switches the Qemu target to use (pseudo) Cache As RAM and enables some ACPI code. This allows to use the CBMEM console and timestamp code with coreboot in Qemu. Right now, the ACPI code is commented out because leaving it in breaks IDE. Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2113 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
13 lines
295 B
Text
13 lines
295 B
Text
chip mainboard/emulation/qemu-x86
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/intel/i82371eb # southbridge
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device pci 01.0 on end
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device pci 01.1 on end
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "gpo" = "0x7fffbbff"
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end
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end
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end
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