coreboot-kgpe-d16/src
Angel Pons 59996e0377 nb/intel/sandybridge: Use one sequence for write leveling
In order to run a write leveling test, one needs to unset the Qoff bit
in MR1, then run the test, and finally set Qoff again. The current IOSAV
sequence uses two subsequences to perform the test, while the other two
are unused. It is possible to perform the two necessary MR1 updates in
the same sequence, which can potentially improve runtime (not measured).

Since `write_mrreg` is no longer used, it is necessary to handle address
mirroring explicitly. This can be accomplished with the recently-added
`ddr3_mirror_mrreg` function, which is also used in `write_mrreg`.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 19:18:57 +00:00
..
acpi ACPI: Define acpi_get_preferred_pm_profile() 2020-11-19 22:58:41 +00:00
arch ACPI S3: Split arch-agnostic parts 2020-11-19 22:58:11 +00:00
commonlib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
console console: Override uart base address 2020-11-09 07:46:10 +00:00
cpu intel/socket_441: Increase bootblock size 2020-11-21 01:53:18 +00:00
device device/pci: Add NULL check for PCI driver's .ops 2020-11-16 12:15:38 +00:00
drivers intel/fsp2_0: Add soc_validate_fsp_version for FSP version check 2020-11-20 18:58:54 +00:00
ec ec/google/chromeec: Add more wrappers for regulator control 2020-11-18 06:13:12 +00:00
include cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
lib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
mainboard mb/google/zork: update berknip CHTC thermal setting 2020-11-22 17:36:25 +00:00
northbridge nb/intel/sandybridge: Use one sequence for write leveling 2020-11-22 19:18:57 +00:00
security cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
soc soc/amd: move non-CAR linker scripts to common directory 2020-11-22 17:35:20 +00:00
southbridge sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs 2020-11-22 14:25:30 +00:00
superio superio/smsc/sio1036: Support 16-bit IO port addressing 2020-11-18 13:12:11 +00:00
vendorcode vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11 2020-11-21 13:52:22 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00