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Kyösti Mälkki 59d609217b AMD fam10: Fix add_more_links
One PCI function may contain upto 4 links, further links must
be added to PCI function 4 on the same device.

There is no requirement that in dev->link_list the last element
would have the highest link->link_num.

Also fix off-by-one error when allocating for more links.

Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8555
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05 10:14:21 +02:00
3rdparty 3rdparty/blobs: Move submodule marker forward 2015-05-13 22:55:50 +02:00
Documentation Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
payloads libpayload: usb: Support MTK xHCI host controller 2015-06-03 11:11:59 +02:00
src AMD fam10: Fix add_more_links 2015-06-05 10:14:21 +02:00
util build system: move more clang handling to xcompile 2015-06-04 20:02:01 +02:00
.gitignore gitignore: Have multiple crossgcc versions 2015-05-25 21:26:02 +02:00
.gitmodules 3rdparty/vboot: Add vboot 2015-05-05 22:49:34 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
MAINTAINERS MAINTAINERS: grab build system responsibility 2015-05-22 22:47:03 +02:00
Makefile build system: move more clang handling to xcompile 2015-06-04 20:02:01 +02:00
Makefile.inc board_id: Remove extra quotes. 2015-06-04 19:01:42 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc build system: move compiler runtime determination to xcompile 2015-06-04 20:01:45 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.