coreboot-kgpe-d16/src/soc
Aaron Durbin 5a4f289c42 tegra124: use the common verstage flow
Though the tegra124 SoC makes their faster cpus come up
in verstage it can still use the common flow. Therefore,
use the common verstage API for performing thenecessary
steps to initialize the caches on the faster cores.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built nyan.

Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11776
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02 12:16:35 +00:00
..
broadcom/cygnus broadcom/cygnus: remove verstage.c 2015-10-02 12:16:21 +00:00
imgtec/pistachio linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
intel intel/fsp_baytrail: Remove unused MICROCODE_INCLUDE_PATH from Kconfig 2015-10-01 13:49:57 +00:00
marvell/bg4cd linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
nvidia tegra124: use the common verstage flow 2015-10-02 12:16:35 +00:00
qualcomm/ipq806x linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
rockchip/rk3288 linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
samsung linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
ucb/riscv Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00