b0f81518b5
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <string.h>
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#include <bootmode.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <ec/compal/ene932/ec.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "ec.h"
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#define GPIO_COUNT 6
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
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if (!gpio_base)
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return;
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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/* Write Protect: GPIO70 active high */
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gpios->gpios[0].port = 70;
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gpios->gpios[0].polarity = ACTIVE_LOW;
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gpios->gpios[0].value = !get_write_protect_state();
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strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH);
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/* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */
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gpios->gpios[1].port = -1;
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gpios->gpios[1].polarity = ACTIVE_HIGH;
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gpios->gpios[1].value = get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
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/* Developer: Virtual GPIO in the EC ( Servo GPIO17 active low) */
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gpios->gpios[2].port = -1;
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gpios->gpios[2].polarity = ACTIVE_HIGH;
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gpios->gpios[2].value = get_developer_mode_switch();
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strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
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/* Lid switch GPIO active high (open). */
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gpios->gpios[3].port = 15;
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gpios->gpios[3].polarity = ACTIVE_HIGH;
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gpios->gpios[3].value = get_lid_switch();
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strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
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/* Power Button */
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gpios->gpios[4].port = 101;
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gpios->gpios[4].polarity = ACTIVE_LOW;
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gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
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strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
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/* Did we load the VGA Option ROM? */
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gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[5].polarity = ACTIVE_HIGH;
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gpios->gpios[5].value = gfx_get_init_done();
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strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
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}
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#endif
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int get_lid_switch(void)
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{
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return get_gpio(15);
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}
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int get_developer_mode_switch(void)
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{
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u8 gpio = !get_gpio(17);
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/*
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* Dev mode is controlled by EC and uboot stores a flag in TPM.
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* This GPIO is only for the debug header.
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* It is AND'd to the EC request.
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*/
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printk(BIOS_DEBUG, "DEV MODE GPIO 17: %x\n", gpio);
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/* GPIO17, active low -- return active high reading and let
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* it be inverted by the caller if needed. */
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return gpio;
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}
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int get_write_protect_state(void)
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{
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return !get_gpio(70);
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}
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int get_recovery_mode_switch(void)
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{
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u8 gpio = !get_gpio(68);
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/* GPIO68, active low. For Servo support
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* Treat as active high and let the caller invert if needed. */
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printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio);
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return gpio;
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}
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int parrot_ec_running_ro(void)
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{
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return !get_gpio(68);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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