3a6550d989
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <timestamp.h>
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#include <cpu/x86/tsc.h>
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#include "pch.h"
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#include <arch/acpi.h>
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#include <console/console.h>
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uint64_t get_initial_timestamp(void)
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{
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tsc_t base_time = {
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.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
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.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
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};
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return tsc_to_uint64(base_time);
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}
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int southbridge_detect_s3_resume(void)
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{
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u32 pm1_cnt;
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u16 pm1_sts;
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
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if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
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return 1;
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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}
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}
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return 0;
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}
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