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Petr Cvek 5adbc767f6 mb/kontron/986lcd-m: Add gameport base allocation workaround
A missing definition of gameport base (PNP io 0x60) will cause
an automatic address assignment during PCI/PNP enumeration, which
won't obey limit 0x7ff. This will cause the enumeration to fail
as other devices already have the values enabled.

The symptoms are: not working USB, PS/2, garbled UART console,
not working PCIe GPUs and crashes. Probably because of wrongly
assigned IO ports.

Example of log (shortened):

Done reading resources.
Setting resources...
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.0 1c *  [0x0 - 0xfff] io
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.1 1c *  [0x1000 - 0x1fff] io
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.2 1c *  [0x2000 - 0x2fff] io
!! Resource didn't fit !!
   aligned base 400 size 10 limit 2e7
   40f needs to be <= 2e7 (limit)
   PCI: 00:1f.2 20 *  [0x3080 - 0x308f] io
!! Resource didn't fit !!
...
ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned
...
ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned
...
PCI: 00:1b.0 subsystem <- 8086/27d8
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 8086/27d0
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 brids70c01mcu0PeC: 0
dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k
MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a
aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h
VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished

We can see the ports probably started to collide after the activation
of 00:1c.0 device. A debug run with compiled SPEW shows the problem
with enumeration:

PCI: 00:1f.1 18 *  [0x50b8 - 0x50bf] io
PCI: 00:1f.2 10 *  [0x50c0 - 0x50c7] io
PCI: 00:1f.2 18 *  [0x50c8 - 0x50cf] io
PCI: 00:1f.1 14 *  [0x50d0 - 0x50d3] io
PCI: 00:1f.1 1c *  [0x50d4 - 0x50d7] io
PCI: 00:1f.2 14 *  [0x50d8 - 0x50db] io
PCI: 00:1f.2 1c *  [0x50dc - 0x50df] io
PNP: 002e.7 60 *  [0x50e0 - 0x50e0] io		<-- gameport base
DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done

Notice a weird base for DOMAIN, along with the limit.

Adding a definition of gameport (0x220) as a workaround fixes
the problems.

The gameport should be still disabled thanks to disable bits
(W83627THF datasheet is little bit chaotic). I didn't find any info
if the gameport is available on some pads of the motherboard.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-01 15:07:13 +00:00
3rdparty 3rdparty/chromeec: Update to latest master 2019-09-16 13:42:10 +00:00
Documentation mb/supermicro: restructure x11ssh-tf to represent a x11 board series 2019-09-26 09:29:25 +00:00
configs configs: Build test CONFIG_BOOTSPLASH 2019-09-27 16:20:16 +00:00
payloads depthcharge: add CONFIG_MAINBOARD_DEPTHCHARGE 2019-09-24 10:34:42 +00:00
src mb/kontron/986lcd-m: Add gameport base allocation workaround 2019-10-01 15:07:13 +00:00
util util/mb/google/hatch: update CRC calculation for correctness 2019-09-30 11:43:28 +00:00
.checkpatch.conf
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules 3rdparty/ffs: add open-power ffs utils 2019-08-25 07:37:11 +00:00
.gitreview
AUTHORS AUTHORS: Move src/device copyrights into AUTHORS file 2019-09-17 08:14:13 +00:00
COPYING
MAINTAINERS MAINTAINERS: Step down as RISC-V maintainer 2019-08-05 22:43:36 +00:00
Makefile coreboot/Makefile: display error when spaces in path of toplevel makefile 2019-09-26 10:11:14 +00:00
Makefile.inc Makefile: Create the build directory before bootblock.bin 2019-09-24 10:36:24 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc Split MAYBE_STATIC to _BSS and _NONZERO variants 2019-08-26 20:56:29 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.