04c5bae390
And move the pre-hardwaremain post code to 0x79 so it comes before hardwaremain at 0x80. Emit these codes from ACPI OS resume vector as well as the finalize step in bd82x6x southbridge. Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
378 lines
11 KiB
C
378 lines
11 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file post_codes.h
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*
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* This aims to be a central point for POST codes used throughout coreboot.
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* All POST codes should be declared here as macros, and post_code() should
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* be used with the macros instead of hardcoded values. This allows us to
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* quicly reference POST codes when nothing is working
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*
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* The format for a POST code macro is
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* #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
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* Lets's keep it at POST_* instead of POST_CODE_*
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*
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* This file is also included by early assembly files. Only use #define s;
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* no function prototypes allowed here
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*
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* DOCUMENTATION:
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* Please document any and all post codes using Doxygen style comments. We
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* want to be able to generate a verbose enough documentation that is useful
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* during debugging. Failure to do so will result in your patch being rejected
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* without any explanation or effort on part of the maintainers.
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*
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*/
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#ifndef POST_CODES_H
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#define POST_CODES_H
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/**
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* \brief Entry into 'crt0.s'. reset code jumps to here
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*
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* First instruction that gets executed after the reset vector jumps.
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* This indicates that the reset vector points to the correct code segment.
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*/
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#define POST_RESET_VECTOR_CORRECT 0x01
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/**
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* \brief Entry into protected mode
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*
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* Preparing to enter protected mode. This is POSTed right before changing to
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* protected mode.
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*/
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#define POST_ENTER_PROTECTED_MODE 0x10
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/**
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* \brief Start copying coreboot to RAM with decompression if compressed
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*
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* POSTed before ramstage is about to be loaded into memory
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*/
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#define POST_PREPARE_RAMSTAGE 0x11
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/**
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* \brief Copy/decompression finished; jumping to RAM
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*
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* This is called after ramstage is loaded in memory, and before
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* the code jumps there. This represents the end of romstage.
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*/
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#define POST_RAMSTAGE_IS_PREPARED 0x12
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/**
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* \brief Entry into c_start
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*
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* c_start.S is the first code executing in ramstage.
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*/
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#define POST_ENTRY_C_START 0x13
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/**
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* \brief Pre call to hardwaremain()
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*
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* POSTed right before hardwaremain is called from c_start.S
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*/
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#define POST_PRE_HARDWAREMAIN 0x79
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/**
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* \brief Entry into coreboot in hardwaremain (RAM)
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*
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* This is the first call in hardwaremain.c. If this code is POSTed, then
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* ramstage has succesfully loaded and started executing.
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*/
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#define POST_ENTRY_RAMSTAGE 0x80
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/**
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* \brief Console is initialized
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*
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* The console is initialized and is ready for usage
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*/
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#define POST_CONSOLE_READY 0x39
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/**
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* \brief Console boot message succeeded
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*
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* First console message has been succesfully sent through the console backend
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* driver.
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*/
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#define POST_CONSOLE_BOOT_MSG 0x40
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/**
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* \brief Before enabling the cache
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*
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* Going to enable the cache
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*/
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#define POST_ENABLING_CACHE 0x60
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/**
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* \brief Devices have been enumerated
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*
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* Bus scan, and device enumeration has completed.
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*/
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#define POST_DEVICE_ENUMERATION_COMPLETE 0x66
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/**
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* \brief Devices have been configured
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*
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* Device confgration has completed.
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*/
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#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88
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/**
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* \brief Devices have been enabled
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*
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* Devices have been enabled.
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*/
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#define POST_DEVICES_ENABLED 0x89
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/**
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* \brief Devices have been initialized
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*
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* Devices have been initialized.
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*/
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#define POST_DEVICES_INITIALIZED 0x8a
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/**
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* \brief Entry into elf boot
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*
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* This POST code is called right before invoking jmp_to_elf_entry()
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* jmp_to_elf_entry() invokes the payload, and should never return
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*/
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#define POST_ENTER_ELF_BOOT 0xf8
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/**
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* \brief Jumping to payload
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*
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* Called right before jumping to a payload. If the boot sequence stops with
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* this code, chances are the payload freezes.
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*/
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#define POST_JUMPING_TO_PAYLOAD 0xf3
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/**
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* \brief Not supposed to get here
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*
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* A function that should not have returned, returned
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*
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* Check the console output for details.
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*/
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#define POST_DEAD_CODE 0xee
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/**
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* \brief Final code before OS resumes
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*
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* Called right before jumping to the OS resume vector.
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*/
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#define POST_OS_RESUME 0xfd
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/**
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* \brief Final code before OS boots
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*
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* This may not be called depending on the payload used.
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*/
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#define POST_OS_BOOT 0xfe
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/**
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* \brief Elfload fail or die() called
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*
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* Coreboot was not able to load the payload, no payload was detected
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* or die() was called.
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* \n
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* If this code appears before entering ramstage, then most likely
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* ramstage is corrupted, and reflashing of the ROM chip is needed.
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* \n
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* If this code appears after ramstage, there is a problem with the payload
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* If the payload was built out-of-tree, check that it was compiled as
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* a coreboot payload
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* \n
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* Check the console output to see exactly where the failure occured.
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*/
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#define POST_DIE 0xff
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/*
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* The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
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* They overlap with previous codes, and most are not even used
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* Some maiboards still require them, but they are deprecated. We want to consolidate
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* our own POST code structure with the codes above.
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*
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* standard AMD post definitions for the AMD Geode
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*/
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#define POST_Output_Port (0x080) /* port to write post codes to*/
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#define POST_preSioInit (0x000)
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#define POST_clockInit (0x001)
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#define POST_CPURegInit (0x002)
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#define POST_UNREAL (0x003)
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#define POST_CPUMemRegInit (0x004)
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#define POST_CPUTest (0x005)
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#define POST_memSetup (0x006)
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#define POST_memSetUpStack (0x007)
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#define POST_memTest (0x008)
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#define POST_shadowRom (0x009)
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#define POST_memRAMoptimize (0x00A)
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#define POST_cacheInit (0x00B)
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#define POST_northBridgeInit (0x00C)
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#define POST_chipsetInit (0x00D)
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#define POST_sioTest (0x00E)
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#define POST_pcATjunk (0x00F)
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#define POST_intTable (0x010)
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#define POST_memInfo (0x011)
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#define POST_romCopy (0x012)
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#define POST_PLLCheck (0x013)
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#define POST_keyboardInit (0x014)
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#define POST_cpuCacheOff (0x015)
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#define POST_BDAInit (0x016)
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#define POST_pciScan (0x017)
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#define POST_optionRomInit (0x018)
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#define POST_ResetLimits (0x019)
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#define POST_summary_screen (0x01A)
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#define POST_Boot (0x01B)
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#define POST_SystemPreInit (0x01C)
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#define POST_ClearRebootFlag (0x01D)
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#define POST_GLIUInit (0x01E)
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#define POST_BootFailed (0x01F)
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#define POST_CPU_ID (0x020)
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#define POST_COUNTERBROKEN (0x021)
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#define POST_DIFF_DIMMS (0x022)
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#define POST_WIGGLE_MEM_LINES (0x023)
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#define POST_NO_GLIU_DESC (0x024)
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#define POST_CPU_LCD_CHECK (0x025)
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#define POST_CPU_LCD_PASS (0x026)
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#define POST_CPU_LCD_FAIL (0x027)
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#define POST_CPU_STEPPING (0x028)
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#define POST_CPU_DM_BIST_FAILURE (0x029)
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#define POST_CPU_FLAGS (0x02A)
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#define POST_CHIPSET_ID (0x02B)
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#define POST_CHIPSET_ID_PASS (0x02C)
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#define POST_CHIPSET_ID_FAIL (0x02D)
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#define POST_CPU_ID_GOOD (0x02E)
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#define POST_CPU_ID_FAIL (0x02F)
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/* PCI config*/
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#define P80_PCICFG (0x030)
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/* PCI io*/
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#define P80_PCIIO (0x040)
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/* PCI memory*/
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#define P80_PCIMEM (0x050)
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/* SIO*/
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#define P80_SIO (0x060)
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/* Memory Setp*/
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#define P80_MEM_SETUP (0x070)
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#define POST_MEM_SETUP (0x070)
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#define ERROR_32BIT_DIMMS (0x071)
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#define POST_MEM_SETUP2 (0x072)
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#define POST_MEM_SETUP3 (0x073)
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#define POST_MEM_SETUP4 (0x074)
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#define POST_MEM_SETUP5 (0x075)
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#define POST_MEM_ENABLE (0x076)
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#define ERROR_NO_DIMMS (0x077)
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#define ERROR_DIFF_DIMMS (0x078)
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#define ERROR_BAD_LATENCY (0x079)
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#define ERROR_SET_PAGE (0x07A)
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#define ERROR_DENSITY_DIMM (0x07B)
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#define ERROR_UNSUPPORTED_DIMM (0x07C)
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#define ERROR_BANK_SET (0x07D)
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#define POST_MEM_SETUP_GOOD (0x07E)
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#define POST_MEM_SETUP_FAIL (0x07F)
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#define POST_UserPreInit (0x080)
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#define POST_UserPostInit (0x081)
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#define POST_Equipment_check (0x082)
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#define POST_InitNVRAMBX (0x083)
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#define POST_NoPIRTable (0x084)
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#define POST_ChipsetFingerPrintPass (0x085)
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#define POST_ChipsetFingerPrintFail (0x086)
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
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#define POST_CPU_FPU_BIST_FAILURE (0x089)
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#define POST_CPU_BTB_BIST_FAILURE (0x08A)
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#define POST_CPU_EX_BIST_FAILURE (0x08B)
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#define POST_Chipset_PI_Test_Fail (0x08C)
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
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#define POST_BIT_CLK_Fail (0x08E)
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#define POST_STACK_SETUP (0x090)
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#define POST_CPU_PF_BIST_FAILURE (0x091)
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#define POST_CPU_L2_BIST_FAILURE (0x092)
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#define POST_CPU_GLCP_BIST_FAILURE (0x093)
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#define POST_CPU_DF_BIST_FAILURE (0x094)
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#define POST_CPU_VG_BIST_FAILURE (0x095)
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#define POST_CPU_VIP_BIST_FAILURE (0x096)
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#define POST_STACK_SETUP_PASS (0x09E)
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#define POST_STACK_SETUP_FAIL (0x09F)
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#define POST_PLL_INIT (0x0A0)
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#define POST_PLL_MANUAL (0x0A1)
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#define POST_PLL_STRAP (0x0A2)
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#define POST_PLL_RESET_FAIL (0x0A3)
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#define POST_PLL_PCI_FAIL (0x0A4)
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#define POST_PLL_MEM_FAIL (0x0A5)
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#define POST_PLL_CPU_VER_FAIL (0x0A6)
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#define POST_MEM_TESTMEM (0x0B0)
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#define POST_MEM_TESTMEM1 (0x0B1)
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#define POST_MEM_TESTMEM2 (0x0B2)
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#define POST_MEM_TESTMEM3 (0x0B3)
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#define POST_MEM_TESTMEM4 (0x0B4)
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#define POST_MEM_TESTMEM_PASS (0x0BE)
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#define POST_MEM_TESTMEM_FAIL (0x0BF)
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#define POST_SECUROM_SECBOOT_START (0x0C0)
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
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#define POST_SECUROM_REMAP_FAIL (0x0C2)
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#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
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#define POST_SECUROM_DCACHESETUP (0x0C4)
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#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
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#define POST_SECUROM_ICACHESETUP (0x0C6)
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#define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
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#define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
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#define POST_SECUROM_PLATFORMSETUP (0x0C9)
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#define POST_SECUROM_SIGCHECKBIOS (0x0CA)
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#define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
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#define POST_SECUROM_PASS (0x0CC)
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#define POST_SECUROM_FAIL (0x0CD)
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#define POST_RCONFInitError (0x0CE)
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#define POST_CacheInitError (0x0CF)
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#define POST_ROM_PREUNCOMPRESS (0x0D0)
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#define POST_ROM_UNCOMPRESS (0x0D1)
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#define POST_ROM_SMM_INIT (0x0D2)
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#define POST_ROM_VID_BIOS (0x0D3)
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#define POST_ROM_LCDINIT (0x0D4)
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#define POST_ROM_SPLASH (0x0D5)
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#define POST_ROM_HDDINIT (0x0D6)
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#define POST_ROM_SYS_INIT (0x0D7)
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#define POST_ROM_DMM_INIT (0x0D8)
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#define POST_ROM_TVINIT (0x0D9)
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#define POST_ROM_POSTUNCOMPRESS (0x0DE)
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#define P80_CHIPSET_INIT (0x0E0)
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#define POST_PreChipsetInit (0x0E1)
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#define POST_LateChipsetInit (0x0E2)
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#define POST_NORTHB_INIT (0x0E8)
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#define POST_INTR_SEG_JUMP (0x0F0)
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#endif /* THE_ALMIGHTY_POST_CODES_H */
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