89a5f0f586
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <drivers/spi/tpm/tpm.h>
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#include <ec/ec.h>
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#include <security/tpm/tss.h>
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#include <soc/soc_chip.h>
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#include <vb2_api.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static void mainboard_update_soc_chip_config(void)
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{
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struct soc_intel_jasperlake_config *cfg = config_of_soc();
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int ret;
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ret = tlcl_lib_init();
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if (ret != VB2_SUCCESS) {
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printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
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return;
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}
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if (!cr50_is_long_interrupt_pulse_enabled()) {
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/* Disable GPIO PM to allow for shorter IRQ pulses */
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printk(BIOS_INFO, "Override GPIO PM\n");
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cfg->gpio_override_pm = 1;
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memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm));
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}
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}
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static void mainboard_init(void *chip_info)
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{
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const struct pad_config *base_pads;
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const struct pad_config *override_pads;
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size_t base_num, override_num;
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base_pads = variant_base_gpio_table(&base_num);
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override_pads = variant_override_gpio_table(&override_num);
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gpio_configure_pads_with_override(base_pads, base_num,
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override_pads, override_num);
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variant_devtree_update();
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if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50))
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mainboard_update_soc_chip_config();
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}
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void __weak variant_devtree_update(void)
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{
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/* Override dev tree settings per board */
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}
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static void mainboard_dev_init(struct device *dev)
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{
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mainboard_ec_init();
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}
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static unsigned long mainboard_write_acpi_tables(
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const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
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{
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return current;
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_dev_init;
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dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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