8a017aa394
Run the command below to fix all occurrences.
git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g'
Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
99 lines
3 KiB
C
99 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 4)
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},
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// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 6)
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},
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// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 7)
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},
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// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 0)
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}
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
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},
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// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
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}
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList,
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};
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->GnbConfig.PsppPolicy = 0;
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}
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERRIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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