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Duncan Laurie 5c026445f0 drivers/intel/wifi: Add support for generating SSDT table
Intel WiFi devices that support wake-on-wifi need to declare a Power
Resource for this wake pin.  Typically this has been done with a
static declaration in the DSDT for each mainboard.  By adding it to
the existing intel/wifi driver it can be done based on a
configuration register in the devicetree.

Additionally the WiFi regulatory domain can be set in the SSDT
directly instead of needing to use NVS to pass the value to the DSDT.

Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that
are found on Chromebooks, and clean up a long line and some comment
formatting.

This was tested by booting on an HP Chromebook 13 device and comparing
that the output in the SSDT matches what used to be in the DSDT.  The
WRDD value is read from VPD, if present, not from devicetree.cb.

Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but
the wifi device is not described in devicetree.cb is tested to ensure
it still generates the AML but does not include the _PRW wake pin.

Example:

devicetree.cb:
  device pci 1c.0 on
    chip drivers/intel/wifi
      register "wake" = "GPE0_DW0_16"
      device pci 00.0 on end
    end
  end

VPD:
  "region"="us"

SSDT.dsl:
  Scope (\_SB.PCI0.RP01) {
    Device (WIFI) {
      Name (_UID, Zero)
      Name (_DDN, "Intel WiFi")
      Name (_ADR, 0x00000000)
      Name (_PRW, Package () { 16, 3 })
      Name (WRDD, Package () {
        Zero,
        Package () {
          0x00000007,
          0x00004150
        }
      })
    }
  }

Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15019
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 05:36:08 +02:00
3rdparty 3rdparty/blobs: add more Qualcomm stubs 2016-05-10 21:22:28 +02:00
Documentation Documentation/Intel/Board: Add Galileo checklist 2016-06-02 02:47:29 +02:00
payloads arm64: Add stack dump to exception handler 2016-05-24 20:51:28 +02:00
src drivers/intel/wifi: Add support for generating SSDT table 2016-06-02 05:36:08 +02:00
util ifwitool: Fix syntax issues with ifwitool 2016-06-01 21:16:45 +02:00
.clang-format
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING update license template. 2006-08-12 22:03:36 +00:00
MAINTAINERS MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb 2016-05-26 23:52:57 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc Makefile: Add ifwitool to list of tools to be built 2016-06-01 21:16:58 +02:00
README
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.