Raul E Rangel 5c124a97aa soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE ... BUG=b:179092979 TEST=boot guybrush and see romstage tag 14:finished loading romstage 2,683,151 (10,079) 1:start of romstage 2,683,159 (8) 970:<unknown> 2,683,386 (227) 15:starting LZMA decompress (ignore for x86) 2,683,391 (5) 16:finished LZMA decompress (ignore for x86) 2,717,867 (34,476) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib8b3fe909140e05a89b74df526bf4f81799ad915 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55398 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-14 18:54:55 +00:00
..
cezanne	soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE	2021-06-14 18:54:55 +00:00
common	soc/amd/common/pi/agesawrapper: use IOAPIC ID defines	2021-06-14 14:52:48 +00:00
picasso	soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE	2021-06-14 18:54:55 +00:00
stoneyridge	soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century	2021-06-11 07:37:43 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00