3f15581faf
There will be no log in cbmem if we trigger ec reset on bootblock stage. Therefore, call dcache_clean_all() before triggering ec reset to flush cache to store logs on cbmem. BUG=b:207743045 TEST=show logs on cbmem Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cache.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <soc/wdt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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/* Writing mode register will clear status register */
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wdt_sta = read32(&mtk_wdt->wdt_status);
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mtk_wdt_clr_status(wdt_sta);
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printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta);
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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printk(BIOS_INFO, "hardware watchdog\n");
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mark_watchdog_tombstone();
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/*
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* We trigger secondary reset by triggering WDT hardware to send signal to EC.
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* We do not use do_board_reset() to send signal to EC
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* which is controlled by software driver.
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* Before triggering secondary reset, clean the data cache so the logs in cbmem
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* console (either in SRAM or DRAM) can be flushed.
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*/
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dcache_clean_all();
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write32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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} else if (wdt_sta & MTK_WDT_STA_SW_RST)
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printk(BIOS_INFO, "normal software reboot\n");
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else if (wdt_sta & MTK_WDT_STA_SPM_RST)
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printk(BIOS_INFO, "SPM reboot\n");
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else if (!wdt_sta)
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printk(BIOS_INFO, "cold boot\n");
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else
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printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta);
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/* Config watchdog reboot mode:
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* Clearing bits:
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* DUAL_MODE & IRQ: trigger reset instead of irq then reset.
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* EXT_POL: select watchdog output signal as active low.
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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clrsetbits32(&mtk_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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return wdt_sta;
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}
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