dcea700762
The raw CPUID is useful for matching the directories under 'src/cpu/intel' and is not easy to find out otherwise because it is most often decoded already. The decoded values are not obviously hexadecimal so prepend them with 0x to make sure they are unambiguous. The output differences look like this: - CPU: Processor Type: 0, Family 6, Model 25, Stepping 2 + CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2 Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4 Signed-off-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3788 Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Tested-by: build bot (Jenkins)
449 lines
16 KiB
C
449 lines
16 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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* written by Stefan Reinauer <stepan@coresystems.de>
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <getopt.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#include "inteltool.h"
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/*
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* http://pci-ids.ucw.cz/read/PC/8086
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* http://en.wikipedia.org/wiki/Intel_Tick-Tock
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* http://en.wikipedia.org/wiki/List_of_Intel_chipsets
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* http://en.wikipedia.org/wiki/Intel_Xeon_chipsets
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*/
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static const struct {
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uint16_t vendor_id, device_id;
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char *name;
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} supported_chips_list[] = {
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/* Host bridges/DRAM controllers (Northbridges) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82946, "946GZ/PL" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
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/* Host bridges /DRAM controllers integrated in CPUs */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" },
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/* Southbridges (LPC controllers) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_DESKTOP, "3400 Desktop" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE, "3400 Mobile" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_P55, "P55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM55, "PM55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H55, "H55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM57, "QM57" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H57, "H57" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM55, "HM55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q57, "Q57" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM57, "HM57" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF, "3400 Mobile SFF" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B55_A, "B55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS57, "QS57" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400, "3400" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3420, "3420" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3450, "3450" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B55_B, "B55" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z68, "Z68" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_P67, "P67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM67, "UM67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65, "HM65" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H67, "H67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM67, "HM67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q65, "Q65" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS67, "QS67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q67, "Q67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM67, "QM67" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B65, "B65" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C202, "C202" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C204, "C204" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C206, "C206" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H61, "H61" },
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{ PCI_VENDOR_ID_INTEL, 0x1d40, "X79" },
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{ PCI_VENDOR_ID_INTEL, 0x1d41, "X79" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z77, "Z77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z75, "Z75" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q77, "Q77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q75, "Q75" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B75, "B75" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H77, "H77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C216, "C216" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM77, "QM77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS77, "QS77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM77, "HM77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM77, "UM77" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM76, "HM76" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" },
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{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
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};
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#ifndef __DARWIN__
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static int fd_mem;
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void *map_physical(uint64_t phys_addr, size_t len)
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{
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void *virt_addr;
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virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) phys_addr);
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if (virt_addr == MAP_FAILED) {
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printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
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phys_addr, len);
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return NULL;
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}
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return virt_addr;
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}
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void unmap_physical(void *virt_addr, size_t len)
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{
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munmap(virt_addr, len);
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}
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#endif
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void print_version(void)
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{
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printf("inteltool v%s -- ", INTELTOOL_VERSION);
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printf("Copyright (C) 2008 coresystems GmbH\n\n");
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printf(
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"This program is free software: you can redistribute it and/or modify\n"
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"it under the terms of the GNU General Public License as published by\n"
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"the Free Software Foundation, version 2 of the License.\n\n"
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"This program is distributed in the hope that it will be useful,\n"
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"but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
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"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
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"GNU General Public License for more details.\n\n"
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"You should have received a copy of the GNU General Public License\n"
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"along with this program. If not, see <http://www.gnu.org/licenses/>.\n\n");
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}
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void print_usage(const char *name)
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{
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printf("usage: %s [-vh?gGrpmedPMa]\n", name);
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printf("\n"
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" -v | --version: print the version\n"
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" -h | --help: print this help\n\n"
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" -g | --gpio: dump soutbridge GPIO registers\n"
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" -G | --gpio-diffs: show GPIO differences from defaults\n"
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" -r | --rcba: dump soutbridge RCBA registers\n"
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" -p | --pmbase: dump soutbridge Power Management registers\n\n"
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" -m | --mchbar: dump northbridge Memory Controller registers\n"
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" -e | --epbar: dump northbridge EPBAR registers\n"
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" -d | --dmibar: dump northbridge DMIBAR registers\n"
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" -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n"
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" -M | --msrs: dump CPU MSRs\n"
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" -A | --ambs: dump AMB registers\n"
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" -a | --all: dump all known registers\n"
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"\n");
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exit(1);
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}
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int main(int argc, char *argv[])
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{
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struct pci_access *pacc;
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struct pci_dev *sb = NULL, *nb, *dev;
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int i, opt, option_index = 0;
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unsigned int id;
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char *sbname = "unknown", *nbname = "unknown";
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int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
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int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
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int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0;
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int show_gpio_diffs = 0;
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static struct option long_options[] = {
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{"version", 0, 0, 'v'},
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{"help", 0, 0, 'h'},
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{"gpios", 0, 0, 'g'},
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{"gpio-diffs", 0, 0, 'G'},
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{"mchbar", 0, 0, 'm'},
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{"rcba", 0, 0, 'r'},
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{"pmbase", 0, 0, 'p'},
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{"epbar", 0, 0, 'e'},
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{"dmibar", 0, 0, 'd'},
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{"pciexpress", 0, 0, 'P'},
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{"msrs", 0, 0, 'M'},
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{"ambs", 0, 0, 'A'},
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{"all", 0, 0, 'a'},
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{0, 0, 0, 0}
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};
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while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA",
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long_options, &option_index)) != EOF) {
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switch (opt) {
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case 'v':
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print_version();
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exit(0);
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break;
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case 'g':
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dump_gpios = 1;
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break;
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case 'G':
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show_gpio_diffs = 1;
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break;
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case 'm':
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dump_mchbar = 1;
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break;
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case 'r':
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dump_rcba = 1;
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break;
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case 'p':
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dump_pmbase = 1;
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break;
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case 'e':
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dump_epbar = 1;
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break;
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case 'd':
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dump_dmibar = 1;
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break;
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case 'P':
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dump_pciexbar = 1;
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break;
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case 'M':
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dump_coremsrs = 1;
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break;
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case 'a':
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dump_gpios = 1;
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show_gpio_diffs = 1;
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dump_mchbar = 1;
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dump_rcba = 1;
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dump_pmbase = 1;
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dump_epbar = 1;
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dump_dmibar = 1;
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dump_pciexbar = 1;
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dump_coremsrs = 1;
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dump_ambs = 1;
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break;
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case 'A':
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dump_ambs = 1;
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break;
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case 'h':
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case '?':
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default:
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print_usage(argv[0]);
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exit(0);
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break;
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}
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}
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#if defined(__FreeBSD__)
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if (open("/dev/io", O_RDWR) < 0) {
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perror("/dev/io");
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#else
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if (iopl(3)) {
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perror("iopl");
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#endif
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printf("You need to be root.\n");
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exit(1);
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}
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#ifndef __DARWIN__
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if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
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perror("Can not open /dev/mem");
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exit(1);
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}
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#endif
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pacc = pci_alloc();
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pci_init(pacc);
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pci_scan_bus(pacc);
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/* Find the required devices */
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for (dev = pacc->devices; dev; dev = dev->next) {
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pci_fill_info(dev, PCI_FILL_CLASS);
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/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
|
|
if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
|
|
if (sb == NULL)
|
|
sb = dev;
|
|
else
|
|
fprintf(stderr, "Multiple devices with class ID"
|
|
" 0x0601, using %02x%02x:%02x.%02x\n",
|
|
dev->domain, dev->bus, dev->dev,
|
|
dev->func);
|
|
}
|
|
}
|
|
|
|
if (!sb) {
|
|
printf("No southbridge found.\n");
|
|
exit(1);
|
|
}
|
|
|
|
pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
|
|
|
|
if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
|
|
printf("Not an Intel(R) southbridge.\n");
|
|
exit(1);
|
|
}
|
|
|
|
nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
|
|
if (!nb) {
|
|
printf("No northbridge found.\n");
|
|
exit(1);
|
|
}
|
|
|
|
pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
|
|
|
|
if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
|
|
printf("Not an Intel(R) northbridge.\n");
|
|
exit(1);
|
|
}
|
|
|
|
id = cpuid(1);
|
|
|
|
/* Intel has suggested applications to display the family of a CPU as
|
|
* the sum of the "Family" and the "Extended Family" fields shown
|
|
* above, and the model as the sum of the "Model" and the 4-bit
|
|
* left-shifted "Extended Model" fields.
|
|
* http://download.intel.com/design/processor/applnots/24161832.pdf
|
|
*/
|
|
printf("CPU: ID 0x%x, Processor Type 0x%x, Family 0x%x, Model 0x%x, Stepping 0x%x\n",
|
|
id, (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
|
|
((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
|
|
|
|
/* Determine names */
|
|
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
|
|
if (nb->device_id == supported_chips_list[i].device_id)
|
|
nbname = supported_chips_list[i].name;
|
|
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
|
|
if (sb->device_id == supported_chips_list[i].device_id)
|
|
sbname = supported_chips_list[i].name;
|
|
|
|
printf("Northbridge: %04x:%04x (%s)\n",
|
|
nb->vendor_id, nb->device_id, nbname);
|
|
|
|
printf("Southbridge: %04x:%04x (%s)\n",
|
|
sb->vendor_id, sb->device_id, sbname);
|
|
|
|
/* Now do the deed */
|
|
|
|
if (dump_gpios) {
|
|
print_gpios(sb, 1, show_gpio_diffs);
|
|
printf("\n\n");
|
|
} else if (show_gpio_diffs) {
|
|
print_gpios(sb, 0, show_gpio_diffs);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_rcba) {
|
|
print_rcba(sb);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_pmbase) {
|
|
print_pmbase(sb, pacc);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_mchbar) {
|
|
print_mchbar(nb, pacc);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_epbar) {
|
|
print_epbar(nb);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_dmibar) {
|
|
print_dmibar(nb);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_pciexbar) {
|
|
print_pciexbar(nb);
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_coremsrs) {
|
|
print_intel_core_msrs();
|
|
printf("\n\n");
|
|
}
|
|
|
|
if (dump_ambs) {
|
|
print_ambs(nb, pacc);
|
|
}
|
|
/* Clean up */
|
|
pci_free_dev(nb);
|
|
// pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
|
|
pci_cleanup(pacc);
|
|
|
|
return 0;
|
|
}
|