coreboot-kgpe-d16/src
Duncan Laurie 5cc51c08cd lynxpoint: Add function for checking for LP chipset
Add a helper function pch_is_lp() that will return 1 if
the current chipset is of the new "low power" variant used
with Haswell ULT.

Additionally these functions are added to SMM so it can
be used there.

Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2811
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 23:05:45 +01:00
..
arch coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE 2013-03-21 22:28:28 +01:00
console Fix race condition building console code 2013-03-21 22:08:05 +01:00
cpu haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option 2013-03-21 23:02:31 +01:00
device ramstage: prepare for relocation 2013-03-21 18:01:38 +01:00
drivers GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
ec Support ITE IT8518 embedded controller running Quanta's firmware 2013-03-14 04:54:21 +01:00
include coreboot: add caching loaded ramstage interface 2013-03-21 22:59:40 +01:00
lib coreboot: add caching loaded ramstage interface 2013-03-21 22:59:40 +01:00
mainboard Supermicro H8SCM: Use SPD read code from F15 wrapper 2013-03-20 05:54:51 +01:00
northbridge haswell: Drop the device ID check in graphics init path 2013-03-21 23:04:07 +01:00
southbridge lynxpoint: Add function for checking for LP chipset 2013-03-21 23:05:45 +01:00
superio Super I/O W83627DHG: Enable UART B by redirecting pins 2013-03-15 17:51:48 +01:00
vendorcode f15tn/Include/OptionIdsInstall.h: Remove idle … || ) 2013-03-20 17:50:02 +01:00
Kconfig coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE 2013-03-21 22:28:28 +01:00