89683c0d26
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium tree to upstream, using google/guado as a baseline. TEST=built and booted tidus with full functionality Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/gpio.h>
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#include <soc/sata.h>
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#define GPIO_SPI_WP 58
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#define GPIO_REC_MODE 12
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#define FLAG_SPI_WP 0
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#define FLAG_REC_MODE 1
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#define FLAG_DEV_MODE 2
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#define GPIO_COUNT 6
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio *gpio;
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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gpio = gpios->gpios;
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fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0);
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fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery",
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get_recovery_mode_switch());
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fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
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get_developer_mode_switch());
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fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
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fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
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fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
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}
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#endif
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int get_write_protect_state(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 2);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
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}
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int get_developer_mode_switch(void)
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{
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return 0;
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}
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int get_recovery_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 2);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
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}
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#ifdef __PRE_RAM__
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void save_chromeos_gpios(void)
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{
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u32 flags = 0;
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/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
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if (get_gpio(GPIO_SPI_WP))
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flags |= (1 << FLAG_SPI_WP);
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/* Recovery: GPIO12 = RECOVERY_L, active low */
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if (!get_gpio(GPIO_REC_MODE))
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flags |= (1 << FLAG_REC_MODE);
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/* Developer: Virtual */
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pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
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}
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#endif
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