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Aaron Durbin 5dc628a2ef util/cbfstool: add machine parseable print
In order to more easily process the output of 'cbfstool print'
with other tools provide a -k option which spits out the
tab-separated header and fields:

Name Offset Type Metadata Size Data Size Total Size

ALIGN_UP(Offset + Total Size, 64) would be the start
of the next entry. Also, one can analzye the overhead
and offsets of each file more easily.

Example output (note: tabs aren't in here):

$ ./coreboot-builds/sharedutils/cbfstool/cbfstool test.serial.bin print
-r FW_MAIN_A  -k
Performing operation on 'FW_MAIN_A' region...
Name	Offset	Type	Metadata Size	Data Size	Total Size
cmos_layout.bin	0x0	cmos_layout	0x38	0x48c	0x4c4
dmic-2ch-48khz-16b.bin	0x500	raw	0x48	0xb68	0xbb0
dmic-2ch-48khz-32b.bin	0x10c0	raw	0x48	0xb68	0xbb0
nau88l25-2ch-48khz-24b.bin	0x1c80	raw	0x48	0x54	0x9c
ssm4567-render-2ch-48khz-24b.bin	0x1d40	raw	0x58	0x54	0xac
ssm4567-capture-4ch-48khz-32b.bin	0x1e00	raw	0x58	0x54	0xac
vbt.bin	0x1ec0	optionrom	0x38	0x1000	0x1038
spd.bin	0x2f00	spd	0x38	0x600	0x638
config	0x3540	raw	0x38	0x1ab7	0x1aef
revision	0x5040	raw	0x38	0x25e	0x296
font.bin	0x5300	raw	0x38	0x77f	0x7b7
vbgfx.bin	0x5ac0	raw	0x38	0x32f8	0x3330
locales	0x8e00	raw	0x28	0x2	0x2a
locale_en.bin	0x8e40	raw	0x38	0x29f6	0x2a2e
u-boot.dtb	0xb880	mrc_cache	0x38	0xff1	0x1029
(empty)	0xc8c0	null	0x64	0xadf4	0xae58
fallback/ramstage	0x17740	stage	0x38	0x15238	0x15270
(empty)	0x2c9c0	null	0x64	0xd2c4	0xd328
fallback/payload	0x39d00	payload	0x38	0x12245	0x1227d
cpu_microcode_blob.bin	0x4bf80	microcode	0x60	0x17000	0x17060
(empty)	0x63000	null	0x28	0x37cf98	0x37cfc0

Change-Id: I1c5f8c1b5f2f980033d6c954c9840299c6268431
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28 19:25:48 +01:00
3rdparty 3rdparty/blobs: Update for latest Carrizo Blobs 2015-12-07 16:10:29 +01:00
Documentation Documentation: Add information about patches from other git repos 2016-01-06 17:41:13 +01:00
payloads payloads: fix dependencies for seabios and filo 2016-01-18 18:57:08 +01:00
src mb/intel/d510mo: Use SATA AHCI by default 2016-01-28 17:57:25 +01:00
util util/cbfstool: add machine parseable print 2016-01-28 19:25:48 +01:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add output files for various make targets 2015-11-24 22:35:34 +01:00
.gitmodules submodules: add arm-trusted-firmware third-party repository 2015-06-23 08:20:24 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail 2015-12-30 20:06:52 +01:00
Makefile Move object files to $(obj)/<class>/ 2016-01-28 00:31:32 +01:00
Makefile.inc Move object files to $(obj)/<class>/ 2016-01-28 00:31:32 +01:00
README README: improve description of compiler requirements 2015-07-30 05:11:33 +02:00
toolchain.inc toolchain.inc: Update comments 2016-01-18 03:58:33 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.