5dd4a20b96
The one issues is the SPD address switch for the second CPU. That means that the memory must be an exact match on each CPU. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
36 lines
876 B
Text
36 lines
876 B
Text
# This will make a target directory of ./VENDOR_MAINBOARD
|
|
|
|
target VENDOR_MAINBOARD
|
|
mainboard VENDOR/MAINBOARD
|
|
|
|
option CC="CROSSCC"
|
|
option CROSS_COMPILE="CROSS_PREFIX"
|
|
option HOSTCC="CROSS_HOSTCC"
|
|
|
|
__COMPRESSION__
|
|
|
|
romimage "normal"
|
|
option USE_FAILOVER_IMAGE=0
|
|
option USE_FALLBACK_IMAGE=0
|
|
option ROM_IMAGE_SIZE=0x20000
|
|
option COREBOOT_EXTRA_VERSION=".0-normal"
|
|
payload __PAYLOAD__
|
|
end
|
|
|
|
romimage "fallback"
|
|
option USE_FAILOVER_IMAGE=0
|
|
option USE_FALLBACK_IMAGE=1
|
|
option ROM_IMAGE_SIZE=0x20000
|
|
option COREBOOT_EXTRA_VERSION=".0-fallback"
|
|
payload __PAYLOAD__
|
|
end
|
|
|
|
romimage "failover"
|
|
option USE_FAILOVER_IMAGE=1
|
|
option USE_FALLBACK_IMAGE=0
|
|
option ROM_IMAGE_SIZE=FAILOVER_SIZE
|
|
option XIP_ROM_SIZE=FAILOVER_SIZE
|
|
option COREBOOT_EXTRA_VERSION=".0-failover"
|
|
end
|
|
|
|
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
|