Felix Held e6dd5dc4ea soc/amd/common/block/graphics: add GPU PCI ID for Barcelo ... Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-17 21:33:17 +00:00
..
dram	device/dram: Add LPDDR4 utilities	2021-06-09 15:10:34 +00:00
azalia.h
azalia_device.h
cardbus.h
device.h	device: Add helper function devfn_disable()	2021-06-17 06:48:45 +00:00
gpio.h
i2c.h
i2c_bus.h
i2c_simple.h
mipi_ids.h	drivers/soundwire/alc1308 : Add ALC1308 soundwire device	2021-02-27 09:41:42 +00:00
mmio.h
path.h	src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPC	2021-07-14 20:24:12 +00:00
pci.h	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
pci_def.h	include/pci_def.h: Add some PCI Power Management CSR bits	2021-06-21 05:30:19 +00:00
pci_ehci.h
pci_ids.h	soc/amd/common/block/graphics: add GPU PCI ID for Barcelo	2021-07-17 21:33:17 +00:00
pci_mmio_cfg.h
pci_ops.h	device: Switch pci_dev_is_wake_source to take pci_devfn_t	2021-05-03 16:28:42 +00:00
pci_rom.h
pci_type.h	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
pciexp.h	device/pciexp_device.c: Remove CPP guarding	2021-03-14 19:27:18 +00:00
pcix.h
pnp.h	device/pnp: Always provide pnp_unset_and_set_config	2021-06-10 05:38:13 +00:00
pnp_def.h
pnp_ops.h
pnp_type.h
resource.h	device: Clean up resource utility function signatures	2021-07-01 09:46:09 +00:00
smbus.h
smbus_def.h
smbus_host.h
soundwire.h
spi.h
xhci.h