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Nick Vaccaro 5df5ade696 mb/google/poppy/variant/nocturne: enable USB acpi
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.

This change produces the following nodes in the SSDT :
    Scope (\_SB.PCI0.XHCI.RHUB.HS01)
    {
        Name (_DDN, "USB Type C Port 1")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS03)
    {
        Name (_DDN, "Bluetooth")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
        {
            GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
                {   // Pin list
                    0x0062
                }
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "reset-gpio",
                    Package (0x04)
                    {
                        \_SB.PCI0.XHCI.RHUB.HS03,
                        Zero,
                        Zero,
                        One
                    }
                }
            }
        })
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS05)
    {
        Name (_DDN, "USB Type C Port 2")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS07)
    {
        Name (_DDN, "POGO")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

BUG=b:119275094
TEST=build and flash to nocturne, log into nocturne and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.

Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
2018-11-22 14:48:15 +00:00
3rdparty 3rdparty/blobs: Update to include QuarkFsp 2018-10-12 23:21:35 +00:00
Documentation Documentation: Add W530 / T530 2018-11-19 09:34:38 +00:00
configs soc/intel/apollolake: Add reset code to postcar stage 2018-10-23 07:11:31 +00:00
payloads payloads/tianocore: rebase patches to UDK2018 release 2018-11-21 15:51:07 +00:00
src mb/google/poppy/variant/nocturne: enable USB acpi 2018-11-22 14:48:15 +00:00
util util/ifdtool: Add IceLake platform support under IFDv2 2018-11-21 13:45:52 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format clang-format: change it to better match our style 2018-07-31 23:25:29 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules submodules: add FSP mirror as non-default submodule 2018-09-02 03:07:50 +00:00
.gitreview
COPYING
MAINTAINERS northbridge/intel/fsp_*: Remove legacy SoCs 2018-11-19 15:43:37 +00:00
Makefile Makefile: Enable DELETE_ON_ERROR for all targets 2018-08-08 21:57:07 +00:00
Makefile.inc build system: Fix FSP downloading 2018-10-27 11:12:09 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.