5e19fa4c51
This is x86 "standard" 0xcf9 reset mechanism. Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5680 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
93 lines
3.1 KiB
C
93 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "agesawrapper.h"
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#include "amdlib.h"
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#include "BiosCallOuts.h"
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#include "heapManager.h"
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#include <northbridge/amd/agesa/family14/dimmSpd.h>
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/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
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*
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* COM Express doesn't provide dedicated resets for individual lanes
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* and it's not needed for the on-board Intel I210 GbE controller.
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*/
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer },
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{AGESA_LOCATE_BUFFER, BiosLocateBuffer },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, BiosReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported },
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{AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit},
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINTN i;
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AGESA_STATUS CalloutStatus;
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UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
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/*
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* printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func);
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*/
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CalloutStatus = AGESA_UNSUPPORTED;
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for (i = 0; i < CallOutCount; i++) {
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if (BiosCallouts[i].CalloutName == Func) {
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CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
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return CalloutStatus;
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}
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}
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return CalloutStatus;
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}
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/* Call the host environment interface to provide a user hook opportunity. */
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AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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MEM_DATA_STRUCT *MemData = ConfigPtr;
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printk(BIOS_INFO, "Setting DDR3 voltage: ");
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FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
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switch (MemData->ParameterListPtr->DDR3Voltage) {
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case VOLT1_25: // board is not able to provide this
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MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
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printk(BIOS_INFO, "can't provide 1.25 V, using ");
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// fall through
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default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
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case VOLT1_35:
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FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
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printk(BIOS_INFO, "1.35 V\n");
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break;
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case VOLT1_5:
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FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
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printk(BIOS_INFO, "1.5 V\n");
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}
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return AGESA_SUCCESS;
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}
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