0867062412
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
58 lines
1.3 KiB
Text
58 lines
1.3 KiB
Text
# Config file for the Total Impact briQ
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# This will make a target directory of ./briq
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target briq
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mainboard totalimpact/briq
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## Use stage 1 initialization code
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option CONFIG_USE_INIT=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option CONFIG_NO_POST=1
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## Enable serial console
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option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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## Boot linux from IDE
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option CONFIG_IDE_PAYLOAD=1
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option CONFIG_IDE_BOOT_DRIVE=0
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option CONFIG_IDE_SWAB=1
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option CONFIG_IDE_OFFSET=0
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# ROM is 1Mb
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option CONFIG_ROM_SIZE=1024*1024
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# Set stack and heap sizes (stage 2)
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option CONFIG_STACK_SIZE=0x10000
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option CONFIG_HEAP_SIZE=0x10000
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# Sandpoint Demo Board
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romimage "normal"
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## Base of ROM
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option CONFIG_ROMBASE=0xfff00000
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## Sandpoint reset vector
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option CONFIG_RESET=CONFIG_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
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## Start of coreboot in the boot rom
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## = CONFIG_RESET + exeception vector table size
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option CONFIG_ROMSTART=CONFIG_RESET+0x3100
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## Coreboot C code runs at this location in RAM
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option CONFIG_RAMBASE=0x00100000
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option CONFIG_RAMSTART=0x00100000
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option CONFIG_BRIQ_750FX=1
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#option CONFIG_BRIQ_7400=1
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end
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buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"
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