38cd29ebd7
produced numerous problems in the past, including the fact that x86emu doesn't work in v3 anymore even though it lives in the v3 repository. Since this is a cross-repository move, keeping the history in the v2 tree would make life hard for everone. So check the v3 repository for x86emu history since the merger. The his commit is based on an svn export of r1175 of the coreboot-v3 repository. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
483 lines
14 KiB
C
483 lines
14 KiB
C
/******************************************************************************
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* Copyright (c) 2004, 2008 IBM Corporation
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* Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
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* All rights reserved.
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* This program and the accompanying materials
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* are made available under the terms of the BSD License
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* which accompanies this distribution, and is available at
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* http://www.opensource.org/licenses/bsd-license.php
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*
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* Contributors:
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* IBM Corporation - initial implementation
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*****************************************************************************/
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#include <types.h>
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#ifdef CONFIG_COREBOOT_V2
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#include "compat/rtas.h"
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#include "compat/time.h"
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#else
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#include <cpu.h>
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#include "rtas.h"
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#include <time.h>
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#endif
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#include "device.h"
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#include "debug.h"
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#include <x86emu/x86emu.h>
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#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#endif
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// those are defined in net-snk/oflib/pci.c
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extern unsigned int read_io(void *, size_t);
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extern int write_io(void *, unsigned int, size_t);
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//defined in net-snk/kernel/timer.c
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extern u64 get_time(void);
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// these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs
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// with the functions and struct below
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void
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outb(u8 val, u16 port)
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{
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printf("WARNING: outb not implemented!\n");
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HALT_SYS();
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}
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void
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outw(u16 val, u16 port)
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{
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printf("WARNING: outw not implemented!\n");
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HALT_SYS();
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}
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void
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outl(u32 val, u16 port)
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{
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printf("WARNING: outl not implemented!\n");
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HALT_SYS();
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}
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u8
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inb(u16 port)
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{
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printf("WARNING: inb not implemented!\n");
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HALT_SYS();
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return 0;
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}
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u16
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inw(u16 port)
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{
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printf("WARNING: inw not implemented!\n");
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HALT_SYS();
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return 0;
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}
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u32
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inl(u16 port)
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{
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printf("WARNING: inl not implemented!\n");
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HALT_SYS();
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return 0;
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}
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u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size);
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void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size);
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u8 handle_port_61h(void);
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u8
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my_inb(X86EMU_pioAddr addr)
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{
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u8 rval = 0xFF;
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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rval = read_io((void *)translated_addr, 1);
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %02x\n", __func__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0x61:
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//8254 KB Controller / Timer Port
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rval = handle_port_61h();
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//DEBUG_PRINTF_IO("%s(%04x) KB / Timer Port B --> %02x\n", __func__, addr, rval);
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return rval;
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break;
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case 0xCFC:
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case 0xCFD:
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case 0xCFE:
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case 0xCFF:
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// PCI Config Mechanism 1 Ports
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return (u8) pci_cfg_read(addr, 1);
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break;
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case 0x0a:
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CHECK_DBG(DEBUG_INTR) {
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X86EMU_trace_on();
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}
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M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
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//HALT_SYS();
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// no break, intentional fall-through to default!!
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__func__, addr);
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rval = *((u8 *) (bios_device.io_buffer + addr));
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %02x\n",
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__func__, addr, rval);
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return rval;
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break;
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}
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}
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}
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u16
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my_inw(X86EMU_pioAddr addr)
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{
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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u16 rval;
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if ((translated_addr & (u64) 0x1) == 0) {
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// 16 bit aligned access...
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u16 tempval = read_io((void *)translated_addr, 2);
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//little endian conversion
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rval = in16le((void *) &tempval);
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} else {
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// unaligned access, read single bytes, little-endian
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rval = (read_io((void *)translated_addr, 1) << 8)
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %04x\n", __func__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFE:
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//PCI Config Mechanism 1
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return (u16) pci_cfg_read(addr, 2);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__func__, addr);
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u16 rval =
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in16le((void *) bios_device.io_buffer + addr);
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %04x\n",
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__func__, addr, rval);
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return rval;
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break;
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}
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}
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}
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u32
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my_inl(X86EMU_pioAddr addr)
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{
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __func__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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u32 rval;
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if ((translated_addr & (u64) 0x3) == 0) {
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// 32 bit aligned access...
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u32 tempval = read_io((void *) translated_addr, 4);
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//little endian conversion
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rval = in32le((void *) &tempval);
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} else {
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// unaligned access, read single bytes, little-endian
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rval = (read_io((void *)(translated_addr), 1) << 24)
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| (read_io((void *)(translated_addr + 1), 1) << 16)
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| (read_io((void *)(translated_addr + 2), 1) << 8)
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %08x\n", __func__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0xCFC:
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//PCI Config Mechanism 1
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return pci_cfg_read(addr, 4);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__func__, addr);
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u32 rval =
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in32le((void *) bios_device.io_buffer + addr);
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %08x\n",
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__func__, addr, rval);
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return rval;
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break;
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}
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}
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}
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void
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my_outb(X86EMU_pioAddr addr, u8 val)
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{
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__func__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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write_io((void *) translated_addr, val, 1);
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %02x\n", __func__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFD:
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case 0xCFE:
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case 0xCFF:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 1);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%02x) writing to bios_device.io_buffer\n",
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__func__, addr, val);
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*((u8 *) (bios_device.io_buffer + addr)) = val;
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break;
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}
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}
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}
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void
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my_outw(X86EMU_pioAddr addr, u16 val)
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{
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__func__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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if ((translated_addr & (u64) 0x1) == 0) {
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// little-endian conversion
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u16 tempval = in16le((void *) &val);
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// 16 bit aligned access...
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write_io((void *) translated_addr, tempval, 2);
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} else {
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// unaligned access, write single bytes, little-endian
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write_io(((void *) (translated_addr + 1)),
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(u8) ((val & 0xFF00) >> 8), 1);
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write_io(((void *) translated_addr),
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(u8) (val & 0x00FF), 1);
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %04x\n", __func__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFE:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 2);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%04x) writing to bios_device.io_buffer\n",
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__func__, addr, val);
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out16le((void *) bios_device.io_buffer + addr, val);
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break;
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}
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}
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}
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void
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my_outl(X86EMU_pioAddr addr, u32 val)
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{
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unsigned long translated_addr = addr;
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u8 translated = biosemu_dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successfull, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__func__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __func__, addr, translated_addr);
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if ((translated_addr & (u64) 0x3) == 0) {
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// little-endian conversion
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u32 tempval = in32le((void *) &val);
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// 32 bit aligned access...
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write_io((void *) translated_addr, tempval, 4);
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} else {
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// unaligned access, write single bytes, little-endian
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write_io(((void *) translated_addr + 3),
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(u8) ((val & 0xFF000000) >> 24), 1);
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write_io(((void *) translated_addr + 2),
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(u8) ((val & 0x00FF0000) >> 16), 1);
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write_io(((void *) translated_addr + 1),
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(u8) ((val & 0x0000FF00) >> 8), 1);
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write_io(((void *) translated_addr),
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(u8) (val & 0x000000FF), 1);
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %08x\n", __func__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 4);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%08x) writing to bios_device.io_buffer\n",
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__func__, addr, val);
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out32le((void *) bios_device.io_buffer + addr, val);
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break;
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}
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}
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}
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u32
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pci_cfg_read(X86EMU_pioAddr addr, u8 size)
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{
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u32 rval = 0xFFFFFFFF;
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struct device * dev;
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later read from 0xCFC-0xCFF returns the value...
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u8 bus, devfn, offs;
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u32 port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
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__func__, bus, devfn, offs);
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#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1
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dev = dev_find_slot(bus, devfn);
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DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n",
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__func__, dev_path(dev));
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if (dev == 0) {
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// fail accesses to non-existent devices...
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#else
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dev = bios_device.dev;
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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#endif
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printf
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("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n",
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__func__, bus, bios_device.bus, devfn,
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bios_device.devfn, offs);
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SET_FLAG(F_CF);
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HALT_SYS();
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return 0;
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} else {
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#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
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switch (size) {
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case 1:
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rval = pci_read_config8(dev, offs);
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break;
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case 2:
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rval = pci_read_config16(dev, offs);
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break;
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case 4:
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rval = pci_read_config32(dev, offs);
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break;
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}
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#else
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rval =
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(u32) rtas_pci_config_read(bios_device.
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puid, size,
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bus, devfn,
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offs);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
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__func__, addr, offs, size, rval);
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}
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}
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}
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return rval;
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}
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void
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pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
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{
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later write to 0xCFC-0xCFF sets the value...
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u8 bus, devfn, offs;
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u32 port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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printf
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("Config write access invalid! PCI device %x:%x.%x, offs: %x\n",
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bus, devfn >> 3, devfn & 7, offs);
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HALT_SYS();
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} else {
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#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
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switch (size) {
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case 1:
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pci_write_config8(bios_device.dev, offs, val);
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break;
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case 2:
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pci_write_config16(bios_device.dev, offs, val);
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break;
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case 4:
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pci_write_config32(bios_device.dev, offs, val);
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break;
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}
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#else
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rtas_pci_config_write(bios_device.puid,
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size, bus, devfn, offs,
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val);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
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__func__, addr, offs, size, val);
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}
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}
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}
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}
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u8
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handle_port_61h(void)
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{
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static u64 last_time = 0;
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u64 curr_time = get_time();
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u64 time_diff; // time since last call
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u32 period_ticks; // length of a period in ticks
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u32 nr_periods; //number of periods passed since last call
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// bit 4 should toggle with every (DRAM) refresh cycle... (66kHz??)
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time_diff = curr_time - last_time;
|
|
// at 66kHz a period is ~ 15 ns long, converted to ticks: (tb_freq is ticks/second)
|
|
// TODO: as long as the frequency does not change, we should not calculate this every time
|
|
period_ticks = (15 * tb_freq) / 1000000;
|
|
nr_periods = time_diff / period_ticks;
|
|
// if the number if ticks passed since last call is odd, we toggle bit 4
|
|
if ((nr_periods % 2) != 0) {
|
|
*((u8 *) (bios_device.io_buffer + 0x61)) ^= 0x10;
|
|
}
|
|
//finally read the value from the io_buffer
|
|
return *((u8 *) (bios_device.io_buffer + 0x61));
|
|
}
|