Felix Held e3adefedca soc/amd/mendocino/acpi: remove RTC wake workaround ... Commit 78ee4889dc ("soc/amd/cezanne/acpi: Add support for RTC workaround") added a workaround for the Cezanne silicon. This was copied to the Mendocino code, but from both the discussion in b:209705576 and the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/ amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true Mendocino doesn't need that workaround, so remove it. TEST=Running suspend_stress_test -c 5 on Chausie shows no errors Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-01-23 19:14:24 +00:00
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cezanne	soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR	2023-01-22 19:08:55 +00:00
common	soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR	2023-01-22 19:08:55 +00:00
glinda	soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR	2023-01-22 19:08:55 +00:00
mendocino	soc/amd/mendocino/acpi: remove RTC wake workaround	2023-01-23 19:14:24 +00:00
phoenix	soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR	2023-01-22 19:08:55 +00:00
picasso	soc/amd/*: Enable override of MAINBOARD_BLOBS_DIR	2023-01-22 19:08:55 +00:00
stoneyridge	soc/amd/stoneyridge,sb/amd/pi/hudson: Remove unused AHCI_ROM_ID	2023-01-22 06:14:54 +00:00