ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
110 lines
2.2 KiB
ArmAsm
110 lines
2.2 KiB
ArmAsm
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/cpu.h>
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/* Disable interrupts and mark the kernel mode */
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.macro setup_c0_status clr
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.set push
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mfc0 $t0, $CP0_STATUS
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or $t0, ST0_CU0 | 0x1f | \clr
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xor $t0, 0x1f | \clr
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mtc0 $t0, $CP0_STATUS
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.set noreorder
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sll $zero, 3
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.set pop
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.endm
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/* Don't reorder instructions */
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.set noreorder
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.align 4
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.global cb_header_ptr
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cb_header_ptr:
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.word 0
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.global old_sp
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old_sp:
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.word 0
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.global _entry, _leave
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.text
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/* Our entry point */
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_entry:
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/*
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* This function saves off the previous stack and switches us to our
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* own execution environment.
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*/
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/* Clear watch and cause registers */
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mtc0 $zero, $CP0_WATCHLO
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mtc0 $zero, $CP0_WATCHHI
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mtc0 $zero, $CP0_CAUSE
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/* Disable interrupts */
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setup_c0_status 0
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/* Don't use at in synthetic instr. */
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.set noat
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/* Init timer */
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mtc0 $zero, $CP0_COUNT
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mtc0 $zero, $CP0_COMPARE
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/* Initialize $gp */
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bal 1f
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nop
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.word _gp
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1:
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lw $gp, 0($ra)
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/* Clear .bss: start_bss = _edata, end_bss = _end */
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la $t0, _edata
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sw $zero, ($t0)
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la $t1, _end - 4
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clear_bss:
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addiu $t0, 4
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sw $zero, ($t0)
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bne $t0, $t1, clear_bss
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nop
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/* Save off the location of the coreboot tables */
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la $at, cb_header_ptr
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sw $a0, 0x00($at)
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/* Save old stack pointer */
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la $at, old_sp
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sw $sp, 0x00($at)
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/* Setup new stack */
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la $sp, _stack
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/* Let's rock */
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la $a2, start_main
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jalr $a2
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nop
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_leave:
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/* Restore old stack. */
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lw $sp, old_sp
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/* Return to the original context. */
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eret
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