ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
98 lines
2.3 KiB
C
98 lines
2.3 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MIPS_ARCH_CACHE_H__
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#define __MIPS_ARCH_CACHE_H__
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#include <stddef.h>
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#include <stdint.h>
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/*
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* Sync primitives
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*/
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/* data memory barrier */
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static inline void dmb(void)
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{
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/* TODO */
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}
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/* data sync barrier */
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static inline void dsb(void)
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{
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/* TODO */
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}
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/* instruction sync barrier */
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static inline void isb(void)
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{
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/* TODO */
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}
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/*
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* Cache maintenance API
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*/
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/* dcache clean and invalidate all */
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void dcache_clean_invalidate_all(void);
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/* dcache clean all */
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void dcache_clean_all(void);
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/* dcache invalidate all (on current level given by CCSELR) */
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void dcache_invalidate_all(void);
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/* returns number of bytes per cache line */
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unsigned int dcache_line_bytes(void);
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/* dcache and MMU disable */
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void dcache_mmu_disable(void);
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/* dcache and MMU enable */
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void dcache_mmu_enable(void);
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/* perform all icache/dcache maintenance needed after loading new code */
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void cache_sync_instructions(void);
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/* tlb invalidate all */
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void tlb_invalidate_all(void);
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/*
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* Generalized setup/init functions
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*/
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/* mmu initialization (set page table address, set permissions, etc) */
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void mmu_init(void);
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enum dcache_policy {
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DCACHE_OFF,
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DCACHE_WRITEBACK,
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DCACHE_WRITETHROUGH,
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};
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/* disable the mmu for a range. Primarily useful to lock out address 0. */
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void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
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/* mmu range configuration (set dcache policy) */
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void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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enum dcache_policy policy);
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#endif /* __MIPS_ARCH_CACHE_H__ */
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