ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* Based on arch/armv7/include/arch/io.h:
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* Copyright 2013 Google Inc.
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MIPS_ARCH_IO_H__
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#define __MIPS_ARCH_IO_H__
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#include <arch/types.h>
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#include <arch/cache.h>
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#include <arch/byteorder.h>
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#define read8(a) (*(volatile uint8_t *) (a))
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#define read16(a) (*(volatile uint16_t *) (a))
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#define read32(a) (*(volatile uint32_t *) (a))
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#define write8(v, a) (*(volatile uint8_t *) (a) = (v))
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#define write16(v, a) (*(volatile uint16_t *) (a) = (v))
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#define write32(v, a) (*(volatile uint32_t *) (a) = (v))
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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* set multiple bits in a register using a single call. These macros can
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* also be used to set a multiple-bit bit pattern using a mask, by
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* specifying the mask in the 'clear' parameter and the new bit pattern
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* in the 'set' parameter.
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*/
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#define out_arch(type, endian, a, v) write##type(cpu_to_##endian(v), a)
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#define in_arch(type, endian, a) endian##_to_cpu(read##type(a))
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#define readb(a) read8(a)
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#define readw(a) read16(a)
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#define readl(a) read32(a)
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#define inb(a) read8(a)
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#define inw(a) read16(a)
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#define inl(a) read32(a)
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#define writeb(v, a) write8(v, a)
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#define writew(v, a) write16(v, a)
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#define writel(v, a) write32(v, a)
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#define outb(v, a) write8(v, a)
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#define outw(v, a) write16(v, a)
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#define outl(v, a) write32(v, a)
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#endif /* __MIPS_ARCH_IO_H__ */
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