571e7f02de
Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
116 lines
2.8 KiB
Text
116 lines
2.8 KiB
Text
config MISSING_BOARD_RESET
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bool
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help
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Selected by boards that don't provide a do_board_reset()
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implementation. This activates a stub that logs the missing
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board reset and halts execution.
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config RAMSTAGE_ADA
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bool
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help
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Selected by features that use Ada code in ramstage.
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config RAMSTAGE_LIBHWBASE
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bool
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select RAMSTAGE_ADA
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help
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Selected by features that require `libhwbase` in ramstage.
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config FLATTENED_DEVICE_TREE
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bool
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help
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Selected by features that require to parse and manipulate a flattened
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devicetree in ramstage.
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config HAVE_SPD_IN_CBFS
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bool
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help
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If enabled, add support for adding spd.hex files in cbfs as spd.bin
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and locating it runtime to load SPD.
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config DIMM_MAX
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int
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default 4
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help
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Total number of memory DIMM slots available on motherboard.
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It is multiplication of number of channel to number of DIMMs per
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channel
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config DIMM_SPD_SIZE
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int
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default 256
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help
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Total SPD size that will be used for DIMM.
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Ex: DDR3 256, DDR4 512.
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config SPD_READ_BY_WORD
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bool
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config SPD_CACHE_IN_FMAP
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bool
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default n
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help
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Enables capability to cache DIMM SPDs in a dedicated FMAP region
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to speed loading of SPD data. Currently requires board-level
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romstage implementation to read/write/utilize cached SPD data.
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When the default FMAP is used, will create a region named RW_SPD_CACHE
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to store the cached SPD data.
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config SPD_CACHE_FMAP_NAME
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string
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depends on SPD_CACHE_IN_FMAP
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default "RW_SPD_CACHE"
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help
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Name of the FMAP region created in the default FMAP to cache SPD data.
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if RAMSTAGE_LIBHWBASE
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config HWBASE_DYNAMIC_MMIO
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def_bool y
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config HWBASE_DEFAULT_MMCONF
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hex
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default ECAM_MMCONF_BASE_ADDRESS
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config HWBASE_DIRECT_PCIDEV
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def_bool y
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endif
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config NO_FMAP_CACHE
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bool
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help
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If your platform really doesn't want to use an FMAP cache (e.g. due to
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space constraints), you can select this to disable warnings and save
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a bit more code.
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config ESPI_DEBUG
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bool
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help
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This option enables eSPI library helper functions for displaying debug
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information.
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config NO_CBFS_MCACHE
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bool
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help
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Disables the CBFS metadata cache. This means that your platform does
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not need to provide a CBFS_MCACHE section in memlayout and can save
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the associated CAR/SRAM size. In that case every single CBFS file
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lookup must re-read the same CBFS directory entries from flash to find
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the respective file.
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config CBFS_CACHE_ALIGN
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int
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default 8
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help
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Sets the alignment of the buffers returned by the cbfs_cache.
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config CBFS_PRELOAD
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bool
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depends on COOP_MULTITASKING
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help
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When enabled it will be possible to preload CBFS files into the
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cbfs_cache. This helps reduce boot time by loading the files
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in the background before they are actually required. This feature
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depends on the read-only boot_device having a DMA controller to
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perform the background transfer.
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