coreboot-kgpe-d16/src/soc/intel/broadwell/acpi/serialio.asl
Duncan Laurie 61680274c1 broadwell: ACPI, romstage, and other updates
broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)

broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)

broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)

broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)

broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)

broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)

broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)

broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)

broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)

broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)

broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)

broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)

broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)

broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)

broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)

Squashed 15 commits for broadwell support.

Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22 03:47:10 +02:00

627 lines
13 KiB
Text

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Intel Serial IO Devices in ACPI Mode
// Serial IO Device BAR0 and BAR1 is 4KB
#define SIO_BAR_LEN 0x1000
// Put SerialIO device in D0 state
// Arg0 - BAR1 of device
// Arg1 - Set if device is in ACPI mode
Method (LPD0, 2, Serialized)
{
// PCI mode devices will be handled by OS PCI bus driver
If (LEqual (Arg1, 0)) {
Return
}
OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
And (SPCS, 0xFFFFFFFC, SPCS)
Store (SPCS, Local0) // Read back after writing
}
// Put SerialIO device in D3 state
// Arg0 - BAR1 of device
// Arg1 - Set if device is in ACPI mode
Method (LPD3, 2, Serialized)
{
// PCI mode devices will be handled by OS PCI bus driver
If (LEqual (Arg1, 0)) {
Return
}
OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Or (SPCS, 0x3, SPCS)
Store (SPCS, Local0) // Read back after writing
}
// Serial IO Resource Consumption for BAR1
Device (SIOR)
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 4)
Name (RBUF, ResourceTemplate()
{
// Serial IO BAR1 (PCI config space) resources
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO
})
// Update BAR1 address and length if set in NVS
Method (_CRS, 0, NotSerialized)
{
// SDMA
If (LNotEqual (\S0B1, Zero)) {
CreateDwordField (^RBUF, ^B1D0._BAS, B0AD)
CreateDwordField (^RBUF, ^B1D0._LEN, B0LN)
Store (\S0B1, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
// I2C0
If (LNotEqual (\S1B1, Zero)) {
CreateDwordField (^RBUF, ^B1D1._BAS, B1AD)
CreateDwordField (^RBUF, ^B1D1._LEN, B1LN)
Store (\S1B1, B1AD)
Store (SIO_BAR_LEN, B1LN)
}
// I2C1
If (LNotEqual (\S2B1, Zero)) {
CreateDwordField (^RBUF, ^B1D2._BAS, B2AD)
CreateDwordField (^RBUF, ^B1D2._LEN, B2LN)
Store (\S2B1, B2AD)
Store (SIO_BAR_LEN, B2LN)
}
// SPI0
If (LNotEqual (\S3B1, Zero)) {
CreateDwordField (^RBUF, ^B1D3._BAS, B3AD)
CreateDwordField (^RBUF, ^B1D3._LEN, B3LN)
Store (\S3B1, B3AD)
Store (SIO_BAR_LEN, B3LN)
}
// SPI1
If (LNotEqual (\S4B1, Zero)) {
CreateDwordField (^RBUF, ^B1D4._BAS, B4AD)
CreateDwordField (^RBUF, ^B1D4._LEN, B4LN)
Store (\S4B1, B4AD)
Store (SIO_BAR_LEN, B4LN)
}
// UART0
If (LNotEqual (\S5B1, Zero)) {
CreateDwordField (^RBUF, ^B1D5._BAS, B5AD)
CreateDwordField (^RBUF, ^B1D5._LEN, B5LN)
Store (\S5B1, B5AD)
Store (SIO_BAR_LEN, B5LN)
}
// UART1
If (LNotEqual (\S6B1, Zero)) {
CreateDwordField (^RBUF, ^B1D6._BAS, B6AD)
CreateDwordField (^RBUF, ^B1D6._LEN, B6LN)
Store (\S6B1, B6AD)
Store (SIO_BAR_LEN, B6LN)
}
// SDIO
If (LNotEqual (\S7B1, Zero)) {
CreateDwordField (^RBUF, ^B1D7._BAS, B7AD)
CreateDwordField (^RBUF, ^B1D7._LEN, B7LN)
Store (\S7B1, B7AD)
Store (SIO_BAR_LEN, B7LN)
}
Return (RBUF)
}
}
Device (SDMA)
{
// Serial IO DMA Controller
Name (_HID, "INTL9C60")
Name (_UID, 1)
Name (_ADR, 0x00150000)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S0B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S0B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
Return (RBUF)
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S0EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
}
Device (I2C0)
{
// Serial IO I2C0 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3432")
}
// LynxPoint-LP
Return ("INT33C2")
}
Name (_UID, 1)
Name (_ADR, 0x00150001)
Name (SSCN, Package () { 432, 507, 9 })
Name (FMCN, Package () { 72, 160, 9 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
})
// DMA channels are only used if Serial IO DMA controller is enabled
Name (DBUF, ResourceTemplate ()
{
FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S1B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S1B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
// Check if Serial IO DMA Controller is enabled
If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
Return (ConcatenateResTemplate (RBUF, DBUF))
} Else {
Return (RBUF)
}
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S1EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S1B1, \S1EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S1B1, \S1EN)
}
}
Device (I2C1)
{
// Serial IO I2C1 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3433")
}
// LynxPoint-LP
Return ("INT33C3")
}
Name (_UID, 1)
Name (_ADR, 0x00150002)
Name (SSCN, Package () { 432, 507, 9 })
Name (FMCN, Package () { 72, 160, 9 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
})
// DMA channels are only used if Serial IO DMA controller is enabled
Name (DBUF, ResourceTemplate ()
{
FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S2B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S2B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
// Check if Serial IO DMA Controller is enabled
If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
Return (ConcatenateResTemplate (RBUF, DBUF))
} Else {
Return (RBUF)
}
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S2EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S2B1, \S2EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S2B1, \S2EN)
}
}
Device (SPI0)
{
// Serial IO SPI0 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3430")
}
// LynxPoint-LP
Return ("INT33C0")
}
Name (_UID, 1)
Name (_ADR, 0x00150003)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S3B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S3B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
Return (RBUF)
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S3EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S3B1, \S3EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S3B1, \S3EN)
}
}
Device (SPI1)
{
// Serial IO SPI1 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3431")
}
// LynxPoint-LP
Return ("INT33C1")
}
Name (_UID, 1)
Name (_ADR, 0x00150004)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
})
// DMA channels are only used if Serial IO DMA controller is enabled
Name (DBUF, ResourceTemplate ()
{
FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S4B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S4B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
// Check if Serial IO DMA Controller is enabled
If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
Return (ConcatenateResTemplate (RBUF, DBUF))
} Else {
Return (RBUF)
}
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S4EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S4B1, \S4EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S4B1, \S4EN)
}
}
Device (UAR0)
{
// Serial IO UART0 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3434")
}
// LynxPoint-LP
Return ("INT33C4")
}
Name (_UID, 1)
Name (_ADR, 0x00150005)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
})
// DMA channels are only used if Serial IO DMA controller is enabled
Name (DBUF, ResourceTemplate ()
{
FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S5B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S5B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
// Check if Serial IO DMA Controller is enabled
If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
Return (ConcatenateResTemplate (RBUF, DBUF))
} Else {
Return (RBUF)
}
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S5EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S5B1, \S5EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S5B1, \S5EN)
}
}
Device (UAR1)
{
// Serial IO UART1 Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3435")
}
// LynxPoint-LP
Return ("INT33C5")
}
Name (_UID, 1)
Name (_ADR, 0x00150006)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S6B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S6B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
Return (RBUF)
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S6EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (\S6B1, \S6EN)
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (\S6B1, \S6EN)
}
}
Device (SDIO)
{
// Serial IO SDIO Controller
Method (_HID)
{
If (\ISWP ()) {
// WildcatPoint
Return ("INT3436")
}
// LynxPoint-LP
Return ("INT33C6")
}
Name (_CID, "PNP0D40")
Name (_UID, 1)
Name (_ADR, 0x00170000)
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
})
Method (_CRS, 0, NotSerialized)
{
// Update BAR0 address and length if set in NVS
If (LNotEqual (\S7B0, Zero)) {
CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
Store (\S7B0, B0AD)
Store (SIO_BAR_LEN, B0LN)
}
Return (RBUF)
}
Method (_STA, 0, NotSerialized)
{
If (LEqual (\S7EN, 0)) {
Return (0x0)
} Else {
Return (0xF)
}
}
}