coreboot-kgpe-d16/src
Nick Vaccaro 60a208e43f mb/google/volteer/variants/eldrid: Add SPD for H5ANAG6NCJR-XNC
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H5ANAG6NCJR-XNC DDR4 memory parts.

BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.

Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12 08:38:36 +00:00
..
acpi acpi: Add SSDT pstate helper functions 2020-09-22 16:06:34 +00:00
arch cpu/qemu-x86/car: Move long mode entry right before c entry 2020-09-29 12:27:04 +00:00
commonlib src/commonlib: Drop unneeded empty lines 2020-09-21 15:53:25 +00:00
console src/console: Drop unneeded empty lines 2020-09-21 15:52:42 +00:00
cpu drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config 2020-10-02 23:11:04 +00:00
device pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
drivers drivers/i2c/nct7802y: Configure remote diodes and local sensor 2020-10-11 11:24:19 +00:00
ec ec/kontron/kempld: Reflow long lines 2020-10-11 11:19:07 +00:00
include pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
lib trogdor: Modify DDR training to use mrc_cache 2020-10-09 19:45:40 +00:00
mainboard mb/google/volteer/variants/eldrid: Add SPD for H5ANAG6NCJR-XNC 2020-10-12 08:38:36 +00:00
northbridge nb/intel/ironlake: Move register headers into a subfolder 2020-10-10 20:00:00 +00:00
security security/intel/txt: Print chipset as hex value 2020-10-08 15:38:19 +00:00
soc util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC 2020-10-12 08:38:27 +00:00
southbridge sb/intel/lynxpoint/pcie.c: fix typo in comment 2020-10-12 08:36:02 +00:00
superio superio/ite: Distinguish between chips for PECI readings 2020-09-22 01:11:02 +00:00
vendorcode vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields 2020-10-08 12:08:31 +00:00
Kconfig sconfig: Allow chipset to provide a base devicetree 2020-10-09 23:25:46 +00:00