377 lines
14 KiB
HTML
377 lines
14 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>Development</title>
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</head>
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<body>
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<h1>Intel® x86 coreboot/FSP Development Process</h1>
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<p>
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The x86 development process for coreboot is broken into the following components:
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</p>
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<ul>
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<li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li>
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<li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li>
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<li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li>
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</ul>
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<p>
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The development process has two main phases:
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</p>
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<ol>
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<li>Minimal coreboot; This phase is single threaded</li>
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<li>Adding coreboot features</li>
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</ol>
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<h2>Minimal coreboot</h2>
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<p>
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The combined steps below describe how to bring up a minimal coreboot for a
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system-on-a-chip (SoC) and a development board:
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</p>
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<table>
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<tr bgcolor="#ffffc0">
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<td>The initial coreboot steps are single threaded!
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The initial minimal FSP development is also single threaded.
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Progress can speed up by adding more developers after the minimal coreboot/FSP
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implementation reaches the payload.
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</td>
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</tr>
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</table>
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<ol>
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<li>Get the necessary tools:
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<ul>
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<li>Linux: Use your package manager to install m4 bison flex and the libcurses development
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package.
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<ul>
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<li>Ubuntu or other Linux distribution that use apt, run:
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<pre><code>sudo apt-get install m4 bison flex libncurses5-dev
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</code></pre>
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</li>
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</ul>
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</li>
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</ul>
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</li>
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<li>Build the cross tools for i386:
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<ul>
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<li>Linux:
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<pre><code>make crossgcc-i386</code></pre>
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To use multiple processors for the toolchain build (which takes a long time), use:
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<pre><code>make crossgcc-i386 CPUS=N</code></pre>
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where N is the number of cores to use for the build.
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</li>
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</ul>
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</li>
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<li>Get something to build:
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<ol type="A">
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<li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
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<li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li>
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<li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li>
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</ol>
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</li>
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<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
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<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
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<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
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<li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
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<li>Enable the serial port
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<ol type="A">
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<li>Power on, enable and configure GPIOs for the
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<a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
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</li>
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<li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
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support to romstage
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</li>
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</ol>
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</li>
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<li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
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<li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
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<li>Enable DRAM:
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<ol type="A">
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<li>Implement the SoC
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<a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
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Support
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</li>
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<li>Implement the board support to read the
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<a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
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</li>
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</ol>
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</li>
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<li>Disable the
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<a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
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</li>
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<li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li>
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<li>
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Implement the .init routine for the
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<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
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structure which calls FSP SiliconInit
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</li>
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<li>
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Start ramstage's
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<a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
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to display the PCI vendor and device IDs
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</li>
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<li>
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Disable the
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<a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
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</li>
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<li>
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Implement the
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<a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
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</li>
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<li>coreboot should now attempt to load the payload</li>
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</ol>
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<h2>Add coreboot Features</h2>
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<p>
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Most of the coreboot development gets done in this phase. Implementation tasks in this
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phase are easily done in parallel.
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</p>
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<ul>
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<li>Payload and OS Features:
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<ul>
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<li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
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<li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
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</ul>
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</li>
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</ul>
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<hr>
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<table border="1">
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<tr bgcolor="#c0ffc0">
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<th colspan=3><h1>Features</h1></th>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>SoC</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>8254 Programmable Interval Timer</td>
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<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
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<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
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</tr>
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<tr>
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<td>8259 Programmable Interrupt Controller</td>
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<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
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<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
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</tr>
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<tr>
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<td>Cache-as-RAM</td>
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<td>
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<a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
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FSP binary:
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
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Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
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called from
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
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Disable: FSP 1.1 TempRamExit called from
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
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</td>
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<td>FindFSP: POST code 0x90
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(<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
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is displayed<br>
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Enable: POST code
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
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is displayed<br>
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Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
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</td>
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</tr>
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<tr>
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<td>Memory Map</td>
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<td>
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Implement a device driver for the
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<a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
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</td>
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<td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
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</tr>
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<tr>
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<td>MTRRs</td>
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<td>
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Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br>
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Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a>
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</td>
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<td>Set: Post code 0x91
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(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>)
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is displayed by
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
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Load: Post code 0x3C is displayed by
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br>
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and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td>
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</tr>
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<tr>
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<td>PCI Device Support</td>
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<td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
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<td>The device is detected by coreboot and usable by the payload</td>
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</tr>
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<tr>
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<td>Ramstage state machine</td>
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<td>
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Implement the chip and domain operations to start the
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<a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
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processing
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</td>
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<td>
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During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
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for the PCI devices on the bus.
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</td>
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</tr>
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<tr>
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<td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
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<td>
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Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
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</td>
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<td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>Board</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>Device Tree</td>
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<td>
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<a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
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the device tree processing<br>
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<a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
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Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
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<td>
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List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
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Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
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Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
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</td>
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</tr>
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<tr>
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<td>DRAM</td>
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<td>
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Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
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UPD Setup:
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<ul>
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<li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
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<li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
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</ul>
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FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a>
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</td>
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<td>Select the following Kconfig values
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<ul>
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<li>DISPLAY_HOBS</li>
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<li>DISPLAY_UPD_DATA</li>
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</ul>
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Testing successful if:
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<ul>
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<li>MemoryInit UPD values are correct</li>
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<li>MemoryInit returns 0 (success) and</li>
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<li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
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is not displayed
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</li>
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</ul>
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</td>
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</tr>
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<tr>
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<td>Serial Port</td>
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<td>
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SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
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Enable: src/soc/mainboard/<Board>/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
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</td>
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<td>Debug serial output works</td>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>Payload</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>ACPI Tables</td>
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<td>
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SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
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</td>
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<td>Verified by payload or OS</td>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>FSP</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>TempRamInit</td>
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<td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
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<td>FSP binary found: POST code 0x90
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(<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
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is displayed<br>
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TempRamInit successful: POST code
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
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is displayed<br>
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</td>
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</tr>
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<tr>
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<td>MemoryInit</td>
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<td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
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<a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
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</td>
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<td>Select the following Kconfig values
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<ul>
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<li>DISPLAY_HOBS</li>
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<li>DISPLAY_UPD_DATA</li>
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</ul>
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Testing successful if:
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<ul>
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<li>MemoryInit UPD values are correct</li>
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<li>MemoryInit returns 0 (success) and</li>
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<li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
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is not displayed
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</li>
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</ul>
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</td>
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</tr>
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<tr>
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<td>TempRamExit</td>
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<td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
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<td>Post code 0x91
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(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
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is displayed before calling TempRamExit by
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
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CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
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Post code 0x39 is displayed by
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
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</td>
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</tr>
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<tr>
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<td>SiliconInit</td>
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<td>
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Implement the .init routine for the
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<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
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</td>
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<td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
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</tr>
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<tr>
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<td>FspNotify</td>
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<td>
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The code which calls FspNotify is located in
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src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
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The fsp_notify_boot_state_callback routine is called three times as specified
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by the BOOT_STATE_INIT_ENTRY macros below the routine.
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</td>
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<td>
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The FspNotify routines are called during:
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<ul>
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<li>BS_DEV_RESOURCES - on exit</li>
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<li>BS_PAYLOAD_LOAD - on exit</li>
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<li>BS_OS_RESUME - on entry (S3 resume)</li>
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</ul>
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</td>
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</tr>
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</table>
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<hr>
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<p>Modified: 4 March 2016</p>
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</body>
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</html> |