230ada6d3c
Clean up and move UART related code under a single uart.c file. Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/uart.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <gpio.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/uart.h>
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#include <soc/bootblock.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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/* Serial IO UART controller legacy mode */
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#define PCR_SERIAL_IO_GPPRVRW7 0x618
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#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
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/* UART2 pad configuration. Support RXD and TXD for now. */
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static const struct pad_config uart2_pads[] = {
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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};
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#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
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uintptr_t uart_platform_base(int idx)
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{
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/* Same base address for all debug port usage. In reality UART2
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* is currently only supported. */
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return UART_BASE_0_ADDR(idx);
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}
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#endif
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void pch_uart_init(void)
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{
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uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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uart_common_init(PCH_DEV_UART2, base);
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/* Put UART2 in byte access mode for 16550 compatibility */
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if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
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pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
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PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
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/*
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* Dummy read after setting any of GPPRVRW7.
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* Required for UART 16550 8-bit Legacy mode to become active
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*/
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lpss_clk_read(base);
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}
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gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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}
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#if !ENV_SMM
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void pch_uart_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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/* Need to set the base and size for the resource allocator. */
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res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
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res->size = UART_DEBUG_BASE_0_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED;
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}
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}
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#endif
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bool pch_uart_init_debug_controller_on_resume(void)
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{
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global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs)
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return !!gnvs->uior;
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return false;
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}
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device_t pch_uart_get_debug_controller(void)
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{
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return PCH_DEV_UART2;
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}
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