Martin Roth dcf86e0cff mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI ... Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2019-10-03 15:29:53 +00:00
..
acpi	cpu/intel/haswell: Rework acpi/cpu.asl	2018-11-30 21:52:00 +00:00
variants	cpu/intel: Enter romstage without BIST	2019-08-18 19:03:22 +00:00
acpi_tables.c	src: Use 'include <string.h>' when appropriate	2019-03-20 20:27:51 +00:00
board_info.txt	Add/Combine Haswell Chromebooks using variant board scheme	2016-12-05 19:06:47 +01:00
chromeos.c	mainboard/google: Remove use of __PRE_RAM__	2019-08-19 00:03:37 +00:00
chromeos.fmd	mainboard: Enable PRESERVE flag in all vboot/chromeos FMD files	2019-03-05 20:52:06 +00:00
cmos.layout	mb/*/*/cmos.layout: Fix the values for the console level	2018-01-26 17:28:56 +00:00
data.vbt	mb/google/slippy: Add a VBT for all variants	2019-01-06 15:39:16 +00:00
dsdt.asl	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
ec.c
ec.h
gma-mainboard.ads
Kconfig	mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI	2019-10-03 15:29:53 +00:00
Kconfig.name
mainboard.c	src/mainboard: Remove unused include <device/pci_ops.h>	2019-09-16 07:29:18 +00:00
Makefile.inc	arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class	2019-07-09 12:43:35 +00:00
onboard.h
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00
smihandler.c	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
thermal.h
variant.h	cpu/intel: Enter romstage without BIST	2019-08-18 19:03:22 +00:00