Aaron Durbin 62f100b028 smm: Update rev 0x30101 SMM revision save state ... According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2013-02-27 03:03:50 +01:00
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amd	AMD Family12h: Fix warnings	2013-02-18 05:01:53 +01:00
intel	Intel: Replace MSR 0xcd with MSR_FSB_FREQ	2013-02-11 20:51:33 +01:00
x86	smm: Update rev 0x30101 SMM revision save state	2013-02-27 03:03:50 +01:00
cpu.h	Unify assembler function handling	2012-12-06 23:13:17 +01:00