239c2e843f
There was a mix of setup code sprinkled across the various components: southbridge code in the northbridge, etc. This commit reorganizes the code so that northbridge code doesn't initialize southbridge components. Additionally, the calling dram initialization no longer calls out to ME code. The main() function in the mainboard calls the necessary ME functions before and after dram initialization. The biggest change is the addition of an early_pch_init() function which initializes the BARs, GPIOs, and RCBA configuration. It is also responsible for reporting back to the caller if the board is being woken up from S3. The one sequence difference is that the RCBA config is performed before claling the reference code. Lastly the rcba configuration was changed to be table driven so that different board/configurations can use the same code. It should be possible to have board/configuration specific gpio and rcba configuration while reusing the romstage code. Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
79 lines
2.5 KiB
Makefile
79 lines
2.5 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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# FIXME, uncomment as soon as we have ME firmware in the blobs repo
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# INTERMEDIATE:=lynxpoint_add_me
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ramstage-y += pch.c
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ramstage-y += azalia.c
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ramstage-y += lpc.c
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ramstage-y += pci.c
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ramstage-y += pcie.c
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ramstage-y += sata.c
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ramstage-y += usb_ehci.c
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ramstage-y += me_9.x.c
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ramstage-y += smbus.c
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ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-y += reset.c early_spi.c
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ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += lp_gpio.c
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ramstage-y += lp_gpio.c
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else
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romstage-y += gpio.c
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ramstage-y += gpio.c
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endif
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lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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PHONY += lynxpoint_add_me
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