f70c1bf69a
If GENERIC_UDELAY is selected don't try to use UDELAY_IO as there will be a udelay() conflict at link time. BUG=b:72378235,b:72170796 Change-Id: I9e01c9daddd0629ecc38a809889b39a505c0e203 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
161 lines
3.7 KiB
Text
161 lines
3.7 KiB
Text
# TODO These two options look too similar
|
|
config PARALLEL_CPU_INIT
|
|
bool
|
|
default n
|
|
|
|
config PARALLEL_MP
|
|
def_bool n
|
|
help
|
|
This option uses common MP infrastructure for bringing up APs
|
|
in parallel. It additionally provides a more flexible mechanism
|
|
for sequencing the steps of bringing up the APs.
|
|
|
|
config PARALLEL_MP_AP_WORK
|
|
def_bool n
|
|
depends on PARALLEL_MP
|
|
help
|
|
Allow APs to do other work after initialization instead of going
|
|
to sleep.
|
|
|
|
config UDELAY_IO
|
|
bool
|
|
default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY
|
|
default n
|
|
|
|
config UDELAY_LAPIC
|
|
bool
|
|
default n
|
|
|
|
config LAPIC_MONOTONIC_TIMER
|
|
def_bool n
|
|
depends on UDELAY_LAPIC
|
|
select HAVE_MONOTONIC_TIMER
|
|
help
|
|
Expose monotonic time using the local APIC.
|
|
|
|
config UDELAY_LAPIC_FIXED_FSB
|
|
int
|
|
|
|
config UDELAY_TSC
|
|
bool
|
|
default n
|
|
|
|
config TSC_CONSTANT_RATE
|
|
def_bool n
|
|
depends on UDELAY_TSC
|
|
help
|
|
This option asserts that the TSC ticks at a known constant rate.
|
|
Therefore, no TSC calibration is required.
|
|
|
|
config TSC_MONOTONIC_TIMER
|
|
def_bool n
|
|
depends on UDELAY_TSC
|
|
select HAVE_MONOTONIC_TIMER
|
|
help
|
|
Expose monotonic time using the TSC.
|
|
|
|
# This option is used in code but never selected.
|
|
config UDELAY_TIMER2
|
|
bool
|
|
default n
|
|
|
|
config TSC_SYNC_LFENCE
|
|
bool
|
|
default n
|
|
help
|
|
The CPU driver should select this if the CPU needs
|
|
to execute an lfence instruction in order to synchronize
|
|
rdtsc. This is true for all modern AMD CPUs.
|
|
|
|
config TSC_SYNC_MFENCE
|
|
bool
|
|
default n
|
|
help
|
|
The CPU driver should select this if the CPU needs
|
|
to execute an mfence instruction in order to synchronize
|
|
rdtsc. This is true for all modern Intel CPUs.
|
|
|
|
config NO_FIXED_XIP_ROM_SIZE
|
|
bool
|
|
default n
|
|
help
|
|
The XIP_ROM_SIZE Kconfig variable is used globally on x86
|
|
with the assumption that all chipsets utilize this value.
|
|
For the chipsets which do not use the variable it can lead
|
|
to unnecessary alignment constraints in cbfs for romstage.
|
|
Therefore, allow those chipsets a path to not be burdened.
|
|
|
|
config XIP_ROM_SIZE
|
|
hex
|
|
depends on !NO_FIXED_XIP_ROM_SIZE
|
|
default ROM_SIZE if ROMCC
|
|
default 0x10000
|
|
|
|
config CPU_ADDR_BITS
|
|
int
|
|
default 36
|
|
|
|
config LOGICAL_CPUS
|
|
bool
|
|
default y
|
|
|
|
config SMM_TSEG
|
|
bool
|
|
default n
|
|
select RELOCATABLE_MODULES
|
|
|
|
config SMM_MODULE_HEAP_SIZE
|
|
hex
|
|
default 0x4000
|
|
depends on SMM_TSEG
|
|
help
|
|
This option determines the size of the heap within the SMM handler
|
|
modules.
|
|
|
|
config SMM_LAPIC_REMAP_MITIGATION
|
|
bool
|
|
default y if NORTHBRIDGE_INTEL_I945
|
|
default y if NORTHBRIDGE_INTEL_GM45
|
|
default y if NORTHBRIDGE_INTEL_NEHALEM
|
|
default n
|
|
|
|
config SERIALIZED_SMM_INITIALIZATION
|
|
bool
|
|
default n
|
|
help
|
|
On some CPUs, there is a race condition in SMM.
|
|
This can occur when both hyperthreads change SMM state
|
|
variables in parallel without coordination.
|
|
Setting this option serializes the SMM initialization
|
|
to avoid an ugly hang in the boot process at the cost
|
|
of a slightly longer boot time.
|
|
|
|
config X86_AMD_FIXED_MTRRS
|
|
bool
|
|
default n
|
|
help
|
|
This option informs the MTRR code to use the RdMem and WrMem fields
|
|
in the fixed MTRR MSRs.
|
|
|
|
config PLATFORM_USES_FSP1_0
|
|
bool
|
|
default n
|
|
help
|
|
Selected for Intel processors/platform combinations that use the
|
|
Intel Firmware Support Package (FSP) 1.0 for initialization.
|
|
|
|
config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
|
|
def_bool n
|
|
help
|
|
On certain platforms a boot speed gain can be realized if mirroring
|
|
the payload data stored in non-volatile storage. On x86 systems the
|
|
payload would typically live in a memory-mapped SPI part. Copying
|
|
the SPI contents to RAM before performing the load can speed up
|
|
the boot process.
|
|
|
|
config SOC_SETS_MSRS
|
|
bool
|
|
default n
|
|
help
|
|
The SoC requires different access methods for reading and writing
|
|
the MSRs. Use SoC specific routines to handle the MSR access.
|