641642e11c
Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65). Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> |
||
|---|---|---|
| .. | ||
| edk2 | ||
| fsp | ||
| Kconfig | ||
| Makefile.inc | ||