64982c5002
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/i2c.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra124/clk_rst.h>
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#include <soc/nvidia/tegra124/gpio.h>
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#include <soc/nvidia/tegra124/pinmux.h>
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#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
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#include "pmic.h"
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static void set_clock_sources(void)
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{
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/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
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writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
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clock_configure_source(mselect, PLLP, 102000);
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/* TODO: is the 1.333MHz correct? This may have always been bogus... */
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clock_configure_source(i2c5, CLK_M, 1333);
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/* TODO: We should be able to set this to 50MHz, but that did not seem
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* reliable. */
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clock_configure_source(sbc4, PLLP, 33333);
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}
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void bootblock_mainboard_init(void)
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{
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set_clock_sources();
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clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
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CLK_H_I2C5 | CLK_H_APBDMA,
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0, CLK_V_MSELECT, 0, 0);
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// Board ID GPIOs, bits 0-3.
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gpio_input(GPIO(Q3));
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gpio_input(GPIO(T1));
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gpio_input(GPIO(X1));
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gpio_input(GPIO(X4));
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// I2C5 (PMU) clock.
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pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
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PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
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// I2C5 (PMU) data.
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pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
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PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
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i2c_init(4);
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pmic_init(4);
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/* SPI4 data out (MOSI) */
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pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
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PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
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PINMUX_PULL_UP);
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/* SPI4 data in (MISO) */
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pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
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PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
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PINMUX_PULL_UP);
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/* SPI4 clock */
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pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
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PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
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/* SPI4 chip select 0 */
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pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
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PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
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tegra_spi_init(4);
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}
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