142 lines
4.3 KiB
C
142 lines
4.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <pc80/i8259.h>
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#include <console/console.h>
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#define MASTER_PIC_ICW1 0x20
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#define SLAVE_PIC_ICW1 0xa0
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#define ICW_SELECT (1 << 4)
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#define OCW_SELECT (0 << 4)
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#define ADI (1 << 2)
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#define SNGL (1 << 1)
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#define IC4 (1 << 0)
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#define MASTER_PIC_ICW2 0x21
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#define SLAVE_PIC_ICW2 0xa1
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#define INT_VECTOR_MASTER 0x20
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#define IRQ0 0x00
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#define IRQ1 0x01
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#define INT_VECTOR_SLAVE 0x28
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#define IRQ8 0x00
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#define IRQ9 0x01
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#define MASTER_PIC_ICW3 0x21
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#define CASCADED_PIC (1 << 2)
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#define MASTER_PIC_ICW4 0x21
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#define SLAVE_PIC_ICW4 0xa1
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#define MICROPROCESSOR_MODE (1 << 0)
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#define SLAVE_PIC_ICW3 0xa1
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#define SLAVE_ID 0x02
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#define MASTER_PIC_OCW1 0x21
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#define SLAVE_PIC_OCW1 0xa1
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#define IRQ2 (1 << 2)
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#define ALL_IRQS 0xff
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#define ELCR1 0x4d0
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#define ELCR2 0x4d1
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void setup_i8259(void)
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{
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/* A write to ICW1 starts the Interrupt Controller Initialization
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* Sequence. This implicitly causes the following to happen:
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* - Interrupt Mask register is cleared
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* - Priority 7 is assigned to IRQ7 input
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* - Slave mode address is set to 7
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* - Special mask mode is cleared
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*
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* We send the initialization sequence to both the master and
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* slave i8259 controller.
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*/
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outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
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outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
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/* Now the interrupt controller expects us to write to ICW2. */
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outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
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outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2);
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/* Now the interrupt controller expects us to write to ICW3.
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*
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* The normal scenario is to set up cascading on IRQ2 on the master
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* i8259 and assign the slave ID 2 to the slave i8259.
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*/
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outb(CASCADED_PIC, MASTER_PIC_ICW3);
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outb(SLAVE_ID, SLAVE_PIC_ICW3);
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/* Now the interrupt controller expects us to write to ICW4.
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*
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* We switch both i8259 to microprocessor mode because they're
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* operating as part of an x86 architecture based chipset
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*/
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outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
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outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
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/* Now clear the interrupts through OCW1.
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* First we mask off all interrupts on the slave interrupt controller
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* then we mask off all interrupts but interrupt 2 on the master
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* controller. This way the cascading stays alife.
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*/
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outb(ALL_IRQS, SLAVE_PIC_OCW1);
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outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
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}
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/**
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* @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller.
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*
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* Switch a certain interrupt to be level / edge triggered.
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*
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* @param int_num legacy interrupt number (3-7, 9-15)
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* @param is_level_triggered 1 for level triggered interrupt, 0 for edge
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* triggered interrupt
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*/
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void i8259_configure_irq_trigger(int int_num, int is_level_triggered)
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{
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u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
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printk(BIOS_SPEW, "%s: current interrupts are 0x%x\n", __func__, int_bits);
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if (is_level_triggered)
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int_bits |= (1 << int_num);
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else
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int_bits &= ~(1 << int_num);
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/* Write new values */
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printk(BIOS_SPEW, "%s: try to set interrupts 0x%x\n", __func__, int_bits);
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outb((u8)(int_bits & 0xff), ELCR1);
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outb((u8)(int_bits >> 8), ELCR2);
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#ifdef PARANOID_IRQ_TRIGGERS
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/* Try reading back the new values. This seems like an error but is not ... */
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if (inb(ELCR1) != (int_bits & 0xff)) {
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printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, (int_bits & 0xff), inb(ELCR1));
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}
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if (inb(ELCR2) != (int_bits >> 8)) {
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printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, (int_bits>>8), inb(ELCR2));
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}
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#endif
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}
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