Michał Żygowski 654a45d2ad src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode ... According to BKDG for AMD Family 16h Models 30h-3Fh Processors SDR50 tuning should be disabled in 0xA8 register. Also fix clock frequency setting in 0xA4 for stepping >= A1 which caused reduced performance of SD cards transfer speed even by half. Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2018-07-10 09:53:22 +00:00
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amd	src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode	2018-07-10 09:53:22 +00:00
broadcom	src: Get rid of unneeded whitespace	2018-06-14 09:32:34 +00:00
intel	src/southbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:31:54 +00:00
nvidia	Remove AMD K8 cpu and northbridge support	2018-05-31 03:42:11 +00:00
ricoh/rl5c476	sb/ricoh/rl5c476: Get rid of device_t	2018-05-21 14:01:49 +00:00
ti	sb/ti/pci{1x2x,i7420,xx12}: Get rid of device_t	2018-05-22 07:18:08 +00:00
via/common	src: Get rid of unneeded whitespace	2018-06-14 09:32:34 +00:00