65ac3d862f
Certain platforms may need to limit their bootblock size to within a given size because specific constraints. Allow the size to be provided by the mainboard or chipset by way of the arch Kconfig being processed after those. Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13691 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
153 lines
3.1 KiB
Text
153 lines
3.1 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009-2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config ARCH_X86
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bool
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default n
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select PCI
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# stage selectors for x86
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config ARCH_BOOTBLOCK_X86_32
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bool
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default n
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select ARCH_X86
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select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
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config ARCH_VERSTAGE_X86_32
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bool
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default n
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config ARCH_ROMSTAGE_X86_32
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bool
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default n
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config ARCH_RAMSTAGE_X86_32
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bool
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default n
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# stage selectors for x64
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config ARCH_BOOTBLOCK_X86_64
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bool
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default n
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select ARCH_X86
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select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
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config ARCH_VERSTAGE_X86_64
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bool
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default n
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config ARCH_ROMSTAGE_X86_64
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bool
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default n
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config ARCH_RAMSTAGE_X86_64
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bool
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default n
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config USE_MARCH_586
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def_bool n
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help
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Allow a platform or processor to select to be compiled using
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the '-march=i586' option instead of the typical '-march=i686'
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# This is an SMP option. It relates to starting up APs.
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# It is usually set in mainboard/*/Kconfig.
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# TODO: Improve description.
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config AP_IN_SIPI_WAIT
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bool
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default n
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depends on ARCH_X86 && SMP
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# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
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# can boot AP CPUs to enable their shared caches.
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config SIPI_VECTOR_IN_ROM
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bool
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default n
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depends on ARCH_X86
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config RAMBASE
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hex
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default 0x100000
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# This is something you almost certainly don't want to mess with.
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# How many SIPIs do we send when starting up APs and cores?
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# The answer in 2000 or so was '2'. Nowadays, on many systems,
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# it is 1. Set a safe default here, and you can override it
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# on reasonable platforms.
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config NUM_IPI_STARTS
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int
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default 2
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config ROMCC
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bool
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default n
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config LATE_CBMEM_INIT
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def_bool n
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help
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Enable this in chipset's Kconfig if northbridge does not implement
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early get_top_of_ram() call for romstage. CBMEM tables will be
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allocated late in ramstage, after PCI devices resources are known.
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config PC80_SYSTEM
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bool
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default y if ARCH_X86
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config BOOTBLOCK_MAINBOARD_INIT
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string
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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config BOOTBLOCK_RESETS
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string
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config HAVE_CMOS_DEFAULT
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def_bool n
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config CMOS_DEFAULT_FILE
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string
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default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
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depends on HAVE_CMOS_DEFAULT
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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config IOAPIC_INTERRUPTS_ON_FSB
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bool
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default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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bool
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default n
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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config ID_SECTION_OFFSET
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hex
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default 0x80
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config COMPILE_IN_DSDT
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bool "compile in DSDT and use that over DSDT in CBFS"
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default n
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# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x10000
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